@@ -293,7 +293,18 @@ ap3_err_t ap3_set_pin_to_analog(uint8_t pinNumber)
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uint8_t funcsel = 0 ;
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am_hal_gpio_pincfg_t pincfg = INPUT;
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- retval = ap3_analog_pad_funcsel (ap3_gpio_pin2pad (pinNumber), &funcsel);
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+ // Handle special ADC channels
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+ if (pinNumber >= ADC_DIFF0 && pinNumber <= ADC_INTERNAL_VSS)
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+ {
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+ // Don't use the pin to pad lookup from the variant file
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+ retval = ap3_analog_pad_funcsel (pinNumber, &funcsel);
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+ }
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+ else
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+ {
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+ // Normal pin lookup
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+ retval = ap3_analog_pad_funcsel (ap3_gpio_pin2pad (pinNumber), &funcsel);
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+ }
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+
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if (retval != AP3_OK)
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{
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return retval;
@@ -355,15 +366,15 @@ ap3_err_t ap3_change_channel(uint8_t padNumber)
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return AP3_OK;
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}
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-
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- bool ap3_pwm_is_running ( uint32_t ui32TimerNumber, uint32_t ui32TimerSegment) {
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+ bool ap3_pwm_is_running ( uint32_t ui32TimerNumber, uint32_t ui32TimerSegment)
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+ {
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volatile uint32_t *pui32ConfigReg;
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bool is_enabled = false ;
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//
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// Find the correct control register.
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//
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- pui32ConfigReg = (uint32_t *)CTIMERADDRn (CTIMER, ui32TimerNumber, CTRL0);
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+ pui32ConfigReg = (uint32_t *)CTIMERADDRn (CTIMER, ui32TimerNumber, CTRL0);
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//
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// Begin critical section while config registers are read and modified.
@@ -378,7 +389,8 @@ bool ap3_pwm_is_running(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment){
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//
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// Check the "enable bit"
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//
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- if ( ui32ConfigVal & (CTIMER_CTRL0_TMRA0EN_Msk | CTIMER_CTRL0_TMRB0EN_Msk) ){
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+ if (ui32ConfigVal & (CTIMER_CTRL0_TMRA0EN_Msk | CTIMER_CTRL0_TMRB0EN_Msk))
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+ {
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is_enabled = true ;
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}
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@@ -390,39 +402,51 @@ bool ap3_pwm_is_running(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment){
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return is_enabled;
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}
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-
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- void ap3_pwm_wait_for_pulse ( uint32_t timer, uint32_t segment, uint32_t output, uint32_t margin) {
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+ void ap3_pwm_wait_for_pulse ( uint32_t timer, uint32_t segment, uint32_t output, uint32_t margin)
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+ {
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volatile uint32_t *pui32CompareReg;
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volatile uint32_t ctimer_val;
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uint32_t cmpr0;
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// Only wait if the ctimer is running to avoid a deadlock
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- if ( ap3_pwm_is_running ( timer, segment) ){
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+ if (ap3_pwm_is_running (timer, segment))
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+ {
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// Get the comapre register address
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- if ( segment == AM_HAL_CTIMER_TIMERA ){
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- if ( output == AM_HAL_CTIMER_OUTPUT_NORMAL ){
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- pui32CompareReg = (uint32_t *)CTIMERADDRn (CTIMER, timer, CMPRA0);
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- }else {
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- pui32CompareReg = (uint32_t *)CTIMERADDRn (CTIMER, timer, CMPRAUXA0);
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+ if (segment == AM_HAL_CTIMER_TIMERA)
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+ {
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+ if (output == AM_HAL_CTIMER_OUTPUT_NORMAL)
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+ {
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+ pui32CompareReg = (uint32_t *)CTIMERADDRn (CTIMER, timer, CMPRA0);
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+ }
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+ else
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+ {
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+ pui32CompareReg = (uint32_t *)CTIMERADDRn (CTIMER, timer, CMPRAUXA0);
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+ }
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+ }
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+ else
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+ {
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+ if (output == AM_HAL_CTIMER_OUTPUT_NORMAL)
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+ {
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+ pui32CompareReg = (uint32_t *)CTIMERADDRn (CTIMER, timer, CMPRB0);
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}
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- }else {
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- if ( output == AM_HAL_CTIMER_OUTPUT_NORMAL ){
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- pui32CompareReg = (uint32_t *)CTIMERADDRn (CTIMER, timer, CMPRB0);
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- }else {
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- pui32CompareReg = (uint32_t *)CTIMERADDRn (CTIMER, timer, CMPRAUXB0);
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+ else
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+ {
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+ pui32CompareReg = (uint32_t *)CTIMERADDRn (CTIMER, timer, CMPRAUXB0);
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}
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}
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// Get the compare value
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cmpr0 = ((uint32_t )(*(pui32CompareReg)) & 0x0000FFFF );
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- if ( cmpr0 ){ // Only wait when cmpr0 is greater than 0 to avoid an infinite while loop
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+ if (cmpr0)
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+ { // Only wait when cmpr0 is greater than 0 to avoid an infinite while loop
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// Wait for the timer value to be less than the compare value so that it is safe to change
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- ctimer_val = am_hal_ctimer_read ( timer, segment);
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- while ( (ctimer_val + 0 ) >= cmpr0 ){
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- ctimer_val = am_hal_ctimer_read ( timer, segment);
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+ ctimer_val = am_hal_ctimer_read (timer, segment);
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+ while ((ctimer_val + 0 ) >= cmpr0)
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+ {
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+ ctimer_val = am_hal_ctimer_read (timer, segment);
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}
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}
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}
@@ -534,16 +558,16 @@ ap3_err_t ap3_pwm_output(uint8_t pin, uint32_t th, uint32_t fw, uint32_t clk)
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if ((th == 0 ) || (fw == 0 ))
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{
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output = AM_HAL_CTIMER_OUTPUT_FORCE0;
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- set_periods = false ; // disable setting periods when going into a forced mode
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+ set_periods = false ; // disable setting periods when going into a forced mode
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}
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else if (th == fw)
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{
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output = AM_HAL_CTIMER_OUTPUT_FORCE1;
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- set_periods = false ; // disable setting periods when going into a forced mode
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+ set_periods = false ; // disable setting periods when going into a forced mode
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}
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// Wait until after high pulse to change the state (avoids inversion)
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- ap3_pwm_wait_for_pulse ( timer, segment, output, 10 );
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+ ap3_pwm_wait_for_pulse (timer, segment, output, 10 );
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// Configure the pin
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am_hal_ctimer_output_config (timer,
@@ -558,7 +582,8 @@ ap3_err_t ap3_pwm_output(uint8_t pin, uint32_t th, uint32_t fw, uint32_t clk)
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// (AM_HAL_CTIMER_FN_PWM_REPEAT | AP3_ANALOG_CLK | AM_HAL_CTIMER_INT_ENABLE) );
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(AM_HAL_CTIMER_FN_PWM_REPEAT | clk));
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- if (set_periods){
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+ if (set_periods)
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+ {
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// If this pad uses secondary output:
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if (output == AM_HAL_CTIMER_OUTPUT_SECONDARY)
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{
@@ -603,17 +628,17 @@ ap3_err_t analogWriteResolution(uint8_t res)
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ap3_err_t analogWrite (uint8_t pin, uint32_t val)
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{
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// Determine the high time based on input value and the current resolution setting
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- uint32_t clk = AM_HAL_CTIMER_HFRC_12MHZ; // Use an Ambiq HAL provided value to select which clock
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- uint32_t fw = 0xFFFF ; // Choose the frame width in clock periods (32767 -> ~ 180 Hz)
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+ uint32_t clk = AM_HAL_CTIMER_HFRC_12MHZ; // Use an Ambiq HAL provided value to select which clock
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+ uint32_t fw = 0xFFFF ; // Choose the frame width in clock periods (32767 -> ~ 180 Hz)
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if (val >= ((0x01 << _analogWriteBits) - 1 ))
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{
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val = fw; // Enable FORCE1
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}
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else
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{
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- val <<= (16 - _analogWriteBits); // Shift over the value to fill available resolution
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+ val <<= (16 - _analogWriteBits); // Shift over the value to fill available resolution
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}
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-
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+
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return ap3_pwm_output (pin, val, fw, clk);
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}
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