Skip to content

Commit 9b77d1d

Browse files
committed
Remove unnecessary code
1 parent f709ac4 commit 9b77d1d

File tree

1 file changed

+1
-12
lines changed

1 file changed

+1
-12
lines changed

compiler/src/dotty/tools/dotc/transform/ReifyQuotes.scala

Lines changed: 1 addition & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -483,18 +483,7 @@ class ReifyQuotes extends MacroTransformWithImplicits {
483483
val captured = mutable.LinkedHashMap.empty[Symbol, Tree]
484484
val captured2 = capturer(captured)
485485

486-
def registerCapturer(sym: Symbol): Unit = capturers.put(sym, captured2)
487-
def forceCapture(sym: Symbol): Unit = captured2(ref(sym))
488-
489-
outer.enteredSyms.foreach(registerCapturer)
490-
491-
if (ctx.owner.owner.is(Inline)) {
492-
registerCapturer(defn.TastyTopLevelSplice_tastyContext)
493-
// Force a macro to have the context in first position
494-
forceCapture(defn.TastyTopLevelSplice_tastyContext)
495-
// Force all parameters of the macro to be created in the definition order
496-
outer.enteredSyms.reverse.foreach(forceCapture)
497-
}
486+
outer.enteredSyms.foreach(sym => capturers.put(sym, captured2))
498487

499488
val tree2 = transform(tree)
500489
capturers --= outer.enteredSyms

0 commit comments

Comments
 (0)