From 128fd0a5b71414f0862c3dfdc19fc389971bb400 Mon Sep 17 00:00:00 2001
From: Nicholas Bishop <nbishop@nbishop.net>
Date: Sun, 5 May 2024 22:04:41 -0400
Subject: [PATCH] Fix risc target_arch cfg

Nightly now checks if target_arch is correct, which revealed a spot where we
used `riscv`, which isn't valid. Switched to test both riscv32 and riscv64.
---
 uefi/src/proto/debug/exception.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/uefi/src/proto/debug/exception.rs b/uefi/src/proto/debug/exception.rs
index ae3852711..4298a54b6 100644
--- a/uefi/src/proto/debug/exception.rs
+++ b/uefi/src/proto/debug/exception.rs
@@ -140,7 +140,7 @@ impl ExceptionType {
     pub const MAX_AARCH64_EXCEPTION: ExceptionType = ExceptionType::EXCEPT_AARCH64_SERROR;
 }
 
-#[cfg(target_arch = "riscv")]
+#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
 impl ExceptionType {
     /// Instruction misaligned
     pub const EXCEPT_RISCV_INST_MISALIGNED: ExceptionType = ExceptionType(0);