Refactor MsiCapability

Author: alesharik

src/capability/msi.rs

@@ -84,34 +84,34 @@ impl MsiCapability {
     }
 
     /// Is MSI capability enabled?
-    pub fn is_enabled<T: ConfigRegionAccess>(&self, access: &T) -> bool {
+    pub fn is_enabled(&self, access: &impl ConfigRegionAccess) -> bool {
         let reg = unsafe { access.read(self.address.address, self.address.offset) };
         reg.get_bit(0)
     }
 
     /// Enable or disable MSI capability
-    pub fn set_enabled<T: ConfigRegionAccess>(&self, enabled: bool, access: &T) {
+    pub fn set_enabled(&self, enabled: bool, access: &impl ConfigRegionAccess) {
         let mut reg = unsafe { access.read(self.address.address, self.address.offset) };
         reg.set_bit(0, enabled);
         unsafe { access.write(self.address.address, self.address.offset, reg) };
     }
 
     /// Set how much interrupts the device will use. If requested count is bigger than supported count,
     /// the second will be used.
-    pub fn set_multiple_message_enable<T: ConfigRegionAccess>(
+    pub fn set_multiple_message_enable(
         &self,
         data: MultipleMessageSupport,
-        access: &T,
+        access: &impl ConfigRegionAccess,
     ) {
         let mut reg = unsafe { access.read(self.address.address, self.address.offset) };
         reg.set_bits(4..7, (data.min(self.multiple_message_capable)) as u32);
         unsafe { access.write(self.address.address, self.address.offset, reg) };
     }
 
     /// Return how much interrupts the device is using
-    pub fn get_multiple_message_enable<T: ConfigRegionAccess>(
+    pub fn get_multiple_message_enable(
         &self,
-        access: &T,
+        access: &impl ConfigRegionAccess,
     ) -> MultipleMessageSupport {
         let reg = unsafe { access.read(self.address.address, self.address.offset) };
         MultipleMessageSupport::try_from(reg.get_bits(4..7) as u8)
@@ -125,12 +125,12 @@ impl MsiCapability {
     /// * `vector` - Which interrupt vector should be triggered on LAPIC
     /// * `trigger_mode` - When interrupt should be triggered
     /// * `access` - PCI Configuration Space accessor
-    pub fn set_message_info<T: ConfigRegionAccess>(
+    pub fn set_message_info(
         &self,
         address: u32,
         vector: u8,
         trigger_mode: TriggerMode,
-        access: &T,
+        access: &impl ConfigRegionAccess,
     ) {
         unsafe { access.write(self.address.address, self.address.offset + 0x4, address) }
         let data_offset = if self.is_64bit { 0xC } else { 0x8 };
@@ -152,7 +152,7 @@ impl MsiCapability {
     /// # Note
     /// Only supported on when device supports 64-bit addressing and per-vector masking. Otherwise
     /// returns `0`
-    pub fn get_message_mask<T: ConfigRegionAccess>(&self, access: &T) -> u32 {
+    pub fn get_message_mask(&self, access: &impl ConfigRegionAccess) -> u32 {
         if self.is_64bit && self.per_vector_masking {
             unsafe { access.read(self.address.address, self.address.offset + 0x10) }
         } else {
@@ -165,7 +165,7 @@ impl MsiCapability {
     /// # Note
     /// Only supported on when device supports 64-bit addressing and per-vector masking. Otherwise
     /// will do nothing
-    pub fn set_message_mask<T: ConfigRegionAccess>(&self, access: &T, mask: u32) {
+    pub fn set_message_mask(&self, access: &impl ConfigRegionAccess, mask: u32) {
         if self.is_64bit && self.per_vector_masking {
             unsafe { access.write(self.address.address, self.address.offset + 0x10, mask) }
         }
@@ -175,7 +175,7 @@ impl MsiCapability {
     ///
     /// # Note
     /// Only supported on when device supports 64-bit addressing. Otherwise will return `0`
-    pub fn get_pending<T: ConfigRegionAccess>(&self, access: &T) -> u32 {
+    pub fn get_pending(&self, access: &impl ConfigRegionAccess) -> u32 {
         if self.is_64bit {
             unsafe { access.read(self.address.address, self.address.offset + 0x14) }
         } else {