From 3b1a95642ba44e1630ba7d001d29630c3116bd77 Mon Sep 17 00:00:00 2001 From: Jonathan 'theJPster' Pallant Date: Sat, 28 Sep 2024 16:38:46 +0100 Subject: [PATCH 1/5] Fix typos in arm-none-eabi.md These arrived in #125690, I think by mistake. --- src/doc/rustc/src/platform-support/arm-none-eabi.md | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/src/doc/rustc/src/platform-support/arm-none-eabi.md b/src/doc/rustc/src/platform-support/arm-none-eabi.md index de0ef322fa673..f135ff155a2ee 100644 --- a/src/doc/rustc/src/platform-support/arm-none-eabi.md +++ b/src/doc/rustc/src/platform-support/arm-none-eabi.md @@ -42,16 +42,15 @@ their own document. There are two 32-bit instruction set architectures (ISAs) defined by Arm: - The [*A32 ISA*][a32-isa], with fixed-width 32-bit instructions. Previously - known as the *Arm* ISA, this originated with the original Arm1 of 1985 and has + known as the *Arm* ISA, this originated with the original ARM1 of 1985 and has been updated by various revisions to the architecture specifications ever since. - The [*T32 ISA*][t32-isa], with a mix of 16-bit and 32-bit width instructions. Note that this term includes both the original 16-bit width *Thumb* ISA introduced with the Armv4T architecture in 1994, and the later 16/32-bit sized - *Thumb-2* ISA introduced with the Armv6T2 architecture in 2003. - -Again, these ISAs have been revised by subsequent revisions to the relevant Arm -architecture specifications. + *Thumb-2* ISA introduced with the Armv6T2 architecture in 2003. Again, these + ISAs have been revised by subsequent revisions to the relevant Arm + architecture specifications. There is also a 64-bit ISA with fixed-width 32-bit instructions called the *A64 ISA*, but targets which implement that instruction set generally start with From 487e8d8350409f4970b74bf06611bd7885a3212a Mon Sep 17 00:00:00 2001 From: Jonathan 'theJPster' Pallant Date: Sat, 28 Sep 2024 18:19:16 +0100 Subject: [PATCH 2/5] Suggested -fpregs instead of +soft-float. Has the same effect, but turning off a feature matches the other flags better than turning on a feature (which actually turns off a feature). --- .../platform-support/thumbv7em-none-eabi.md | 15 ++++++--- .../thumbv8m.main-none-eabi.md | 31 ++++++++++++------- 2 files changed, 30 insertions(+), 16 deletions(-) diff --git a/src/doc/rustc/src/platform-support/thumbv7em-none-eabi.md b/src/doc/rustc/src/platform-support/thumbv7em-none-eabi.md index f25ef0383b185..7436a4a53b172 100644 --- a/src/doc/rustc/src/platform-support/thumbv7em-none-eabi.md +++ b/src/doc/rustc/src/platform-support/thumbv7em-none-eabi.md @@ -35,9 +35,9 @@ to use these flags. | CPU | FPU | DSP | Target CPU | Target Features | | ---------- | --- | --- | ----------- | --------------- | | Any | No | Yes | None | None | -| Cortex-M4 | No | Yes | `cortex-m4` | `+soft-float` | +| Cortex-M4 | No | Yes | `cortex-m4` | `-fpregs` | | Cortex-M4F | SP | Yes | `cortex-m4` | None | -| Cortex-M7 | No | Yes | `cortex-m7` | `+soft-float` | +| Cortex-M7 | No | Yes | `cortex-m7` | `-fpregs` | | Cortex-M7F | SP | Yes | `cortex-m7` | `-fp64` | | Cortex-M7F | DP | Yes | `cortex-m7` | None | @@ -50,6 +50,13 @@ to use these flags. | Cortex-M7F | SP | Yes | `cortex-m7` | `-fp64` | | Cortex-M7F | DP | Yes | `cortex-m7` | None | +
+ +Never use the `-fpregs` *target-feature* with these `eabihf` targets +as it will cause compilation units to have different ABIs, which is unsound. + +
+ ### Arm Cortex-M4 and Arm Cortex-M4F The target CPU is `cortex-m4`. @@ -59,7 +66,7 @@ The target CPU is `cortex-m4`. * enabled by default with this *target* * Cortex-M4F has a single precision FPU * support is enabled by default with this *target-cpu* - * disable support using the `+soft-float` feature (`eabi` only) + * disable support using the `-fpregs` *target-feature* (`eabi` only) ### Arm Cortex-M7 and Arm Cortex-M7F @@ -71,4 +78,4 @@ The target CPU is `cortex-m7`. * Cortex-M7F have either a single-precision or double-precision FPU * double-precision support is enabled by default with this *target-cpu* * opt-out by using the `-f64` *target-feature* - * disable support entirely using the `+soft-float` feature (`eabi` only) + * disable support entirely using the `-fpregs` *target-feature* (`eabi` only) diff --git a/src/doc/rustc/src/platform-support/thumbv8m.main-none-eabi.md b/src/doc/rustc/src/platform-support/thumbv8m.main-none-eabi.md index 4e696f9c30461..7d4abfc8485c0 100644 --- a/src/doc/rustc/src/platform-support/thumbv8m.main-none-eabi.md +++ b/src/doc/rustc/src/platform-support/thumbv8m.main-none-eabi.md @@ -39,22 +39,22 @@ to use these flags. | CPU | FPU | DSP | MVE | Target CPU | Target Features | | ----------- | --- | --- | --------- | ------------- | --------------------- | | Unspecified | No | No | No | None | None | -| Cortex-M33 | No | No | No | `cortex-m33` | `+soft-float,-dsp` | -| Cortex-M33 | No | Yes | No | `cortex-m33` | `+soft-float` | +| Cortex-M33 | No | No | No | `cortex-m33` | `-fpregs,-dsp` | +| Cortex-M33 | No | Yes | No | `cortex-m33` | `-fpregs` | | Cortex-M33 | SP | No | No | `cortex-m33` | `-dsp` | | Cortex-M33 | SP | Yes | No | `cortex-m33` | None | -| Cortex-M35P | No | No | No | `cortex-m35p` | `+soft-float,-dsp` | -| Cortex-M35P | No | Yes | No | `cortex-m35p` | `+soft-float` | +| Cortex-M35P | No | No | No | `cortex-m35p` | `-fpregs,-dsp` | +| Cortex-M35P | No | Yes | No | `cortex-m35p` | `-fpregs` | | Cortex-M35P | SP | No | No | `cortex-m35p` | `-dsp` | | Cortex-M35P | SP | Yes | No | `cortex-m35p` | None | -| Cortex-M55 | No | Yes | No | `cortex-m55` | `+soft-float,-mve` | +| Cortex-M55 | No | Yes | No | `cortex-m55` | `-fpregs,-mve` | | Cortex-M55 | DP | Yes | No | `cortex-m55` | `-mve` | -| Cortex-M55 | No | Yes | Int | `cortex-m55` | `+soft-float,-mve.fp` | +| Cortex-M55 | No | Yes | Int | `cortex-m55` | `-fpregs,-mve.fp,+mve`| | Cortex-M55 | DP | Yes | Int | `cortex-m55` | `-mve.fp` | | Cortex-M55 | DP | Yes | Int+Float | `cortex-m55` | None | -| Cortex-M85 | No | Yes | No | `cortex-m85` | `+soft-float,-mve` | +| Cortex-M85 | No | Yes | No | `cortex-m85` | `-fpregs,-mve` | | Cortex-M85 | DP | Yes | No | `cortex-m85` | `-mve` | -| Cortex-M85 | No | Yes | Int | `cortex-m85` | `+soft-float,-mve.fp` | +| Cortex-M85 | No | Yes | Int | `cortex-m85` | `-fpregs,-mve.fp,+mve`| | Cortex-M85 | DP | Yes | Int | `cortex-m85` | `-mve.fp` | | Cortex-M85 | DP | Yes | Int+Float | `cortex-m85` | None | @@ -74,6 +74,13 @@ to use these flags. | Cortex-M85 | DP | Yes | Int | `cortex-m85` | `-mve.fp` | | Cortex-M85 | DP | Yes | Int+Float | `cortex-m85` | None | +
+ +Never use the `-fpregs` *target-feature* with these `eabihf` targets +as it will cause compilation units to have different ABIs, which is unsound. + +
+ ### Arm Cortex-M33 The target CPU is `cortex-m33`. @@ -83,7 +90,7 @@ The target CPU is `cortex-m33`. * enabled by default with this *target-cpu* * Has an optional single precision FPU * support is enabled by default with this *target-cpu* - * disable support using the `+soft-float` feature (`eabi` only) + * disable support using the `-fpregs` *target-feature* (`eabi` only) ### Arm Cortex-M35P @@ -94,7 +101,7 @@ The target CPU is `cortex-m35p`. * enabled by default with this *target-cpu* * Has an optional single precision FPU * support is enabled by default with this *target-cpu* - * disable support using the `+soft-float` feature (`eabi` only) + * disable support using the `-fpregs` *target-feature* (`eabi` only) ### Arm Cortex-M55 @@ -106,7 +113,7 @@ The target CPU is `cortex-m55`. * Has an optional double-precision FPU that also supports half-precision FP16 values * support is enabled by default with this *target-cpu* - * disable support using the `+soft-float` feature (`eabi` only) + * disable support using the `-fpregs` *target-feature* (`eabi` only) * Has optional support for M-Profile Vector Extensions * Also known as *Helium Technology* * Available with only integer support, or both integer/float support @@ -125,7 +132,7 @@ The target CPU is `cortex-m85`. * Has an optional double-precision FPU that also supports half-precision FP16 values * support is enabled by default with this *target-cpu* - * disable support using the `+soft-float` feature (`eabi` only) + * disable support using the `-fpregs` *target-feature* (`eabi` only) * Has optional support for M-Profile Vector Extensions * Also known as *Helium Technology* * Available with only integer support, or both integer/float support From 1bec0226d9ec3cf12d1709daa6b23e9f16f08d10 Mon Sep 17 00:00:00 2001 From: Jonathan 'theJPster' Pallant Date: Sat, 28 Sep 2024 18:20:12 +0100 Subject: [PATCH 3/5] Add warning to arm-none-eabi.md instead of a Note: --- src/doc/rustc/src/platform-support/arm-none-eabi.md | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/doc/rustc/src/platform-support/arm-none-eabi.md b/src/doc/rustc/src/platform-support/arm-none-eabi.md index f135ff155a2ee..9732df4be7f72 100644 --- a/src/doc/rustc/src/platform-support/arm-none-eabi.md +++ b/src/doc/rustc/src/platform-support/arm-none-eabi.md @@ -105,10 +105,14 @@ features you do not have available, leaving you with the optimized instruction scheduling and support for the features you do have. More details are available in the detailed target-specific documentation. -**Note:** Many target-features are currently unstable and subject to change, and +
+ +Many target-features are currently unstable and subject to change, and if you use them you should disassemble the compiler output and manually inspect it to ensure only appropriate instructions for your CPU have been generated. +
+ If you wish to use the *target-cpu* and *target-feature* options, you can add them to your `.cargo/config.toml` file alongside any other flags your project uses (likely linker related ones): From b52941dec76656f9c80c5f67e5326fafd256b9e0 Mon Sep 17 00:00:00 2001 From: Jonathan 'theJPster' Pallant Date: Fri, 11 Oct 2024 13:54:18 +0200 Subject: [PATCH 4/5] Clarify wording around use of `-fpregs` for amr platform docs. --- src/doc/rustc/src/platform-support/thumbv7em-none-eabi.md | 2 +- .../rustc/src/platform-support/thumbv8m.main-none-eabi.md | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/doc/rustc/src/platform-support/thumbv7em-none-eabi.md b/src/doc/rustc/src/platform-support/thumbv7em-none-eabi.md index 7436a4a53b172..11c9486cb76ea 100644 --- a/src/doc/rustc/src/platform-support/thumbv7em-none-eabi.md +++ b/src/doc/rustc/src/platform-support/thumbv7em-none-eabi.md @@ -52,7 +52,7 @@ to use these flags.
-Never use the `-fpregs` *target-feature* with these `eabihf` targets +Never use the `-fpregs` *target-feature* with the `thumbv7em-none-eabihf` target as it will cause compilation units to have different ABIs, which is unsound.
diff --git a/src/doc/rustc/src/platform-support/thumbv8m.main-none-eabi.md b/src/doc/rustc/src/platform-support/thumbv8m.main-none-eabi.md index 7d4abfc8485c0..40b19364f61c2 100644 --- a/src/doc/rustc/src/platform-support/thumbv8m.main-none-eabi.md +++ b/src/doc/rustc/src/platform-support/thumbv8m.main-none-eabi.md @@ -76,8 +76,9 @@ to use these flags.
-Never use the `-fpregs` *target-feature* with these `eabihf` targets -as it will cause compilation units to have different ABIs, which is unsound. +Never use the `-fpregs` *target-feature* with the `thumbv8m.main-none-eabihf` +target as it will cause compilation units to have different ABIs, which is +unsound.
From 5cc1c7b594d97245d2feffbe14478b15f4e48db8 Mon Sep 17 00:00:00 2001 From: Jonathan 'theJPster' Pallant Date: Fri, 11 Oct 2024 13:55:17 +0200 Subject: [PATCH 5/5] Note Integer MVE hard-float use-case in arm platform docs. --- .../rustc/src/platform-support/thumbv8m.main-none-eabi.md | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/doc/rustc/src/platform-support/thumbv8m.main-none-eabi.md b/src/doc/rustc/src/platform-support/thumbv8m.main-none-eabi.md index 40b19364f61c2..82fdc5b21cf2d 100644 --- a/src/doc/rustc/src/platform-support/thumbv8m.main-none-eabi.md +++ b/src/doc/rustc/src/platform-support/thumbv8m.main-none-eabi.md @@ -74,6 +74,11 @@ to use these flags. | Cortex-M85 | DP | Yes | Int | `cortex-m85` | `-mve.fp` | | Cortex-M85 | DP | Yes | Int+Float | `cortex-m85` | None | +*Technically* you can use this hard-float ABI on a CPU which has no FPU but does +have Integer MVE, because MVE provides the same set of registers as the FPU +(including `s0` and `d0`). The particular set of flags that might enable this +unusual scenario are currently not recorded here. +
Never use the `-fpregs` *target-feature* with the `thumbv8m.main-none-eabihf`