diff --git a/library/core/src/convert/num.rs b/library/core/src/convert/num.rs
index 56ab63be27d37..b048b51359208 100644
--- a/library/core/src/convert/num.rs
+++ b/library/core/src/convert/num.rs
@@ -142,9 +142,9 @@ impl_from! { i16, isize, #[stable(feature = "lossless_iusize_conv", since = "1.2
 
 // RISC-V defines the possibility of a 128-bit address space (RV128).
 
-// CHERI proposes 256-bit “capabilities”. Unclear if this would be relevant to usize/isize.
+// CHERI proposes 128-bit “capabilities”. Unclear if this would be relevant to usize/isize.
 // https://www.cl.cam.ac.uk/research/security/ctsrd/pdfs/20171017a-cheri-poster.pdf
-// https://www.csl.sri.com/users/neumann/2012resolve-cheri.pdf
+// https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-951.pdf
 
 // Note: integers can only be represented with full precision in a float if
 // they fit in the significand, which is 24 bits in f32 and 53 bits in f64.