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Issues: rust-lang/rust

Draft release notes for 1.88.0
#141598 opened May 26, 2025 by Mark-Simulacrum
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Issues list

LLVM Assertion failed when optimizing SIMD code on aarch64.apple.darwin A-LLVM Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues. A-SIMD Area: SIMD (Single Instruction Multiple Data) C-bug Category: This is a bug. I-ICE Issue: The compiler panicked, giving an Internal Compilation Error (ICE) ❄️ O-apple Operating system: Apple (macOS, iOS, tvOS, visionOS, watchOS) T-compiler Relevant to the compiler team, which will review and decide on the PR/issue.
#140933 opened May 12, 2025 by bk-eclipse
6
Tracking Issue for AVX10 target features A-SIMD Area: SIMD (Single Instruction Multiple Data) A-target-feature Area: Enabling/disabling target features like AVX, Neon, etc. C-tracking-issue Category: An issue tracking the progress of sth. like the implementation of an RFC O-x86_32 Target: x86 processors, 32 bit (like i686-*) (IA-32) O-x86_64 Target: x86-64 processors (like x86_64-*) (also known as amd64 and x64) T-libs-api Relevant to the library API team, which will review and decide on the PR/issue.
#138843 opened Mar 22, 2025 by sayantn
With LLVM 20 the SIMD intrinsic wasm32::u8x16_sub_sat is compiled to a function call A-LLVM Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues. A-SIMD Area: SIMD (Single Instruction Multiple Data) C-bug Category: This is a bug. O-wasm Target: WASM (WebAssembly), http://webassembly.org/
#137419 opened Feb 22, 2025 by hkratz
1
3
Bad codegen for widen followed by ARM vdupq_n_* A-SIMD Area: SIMD (Single Instruction Multiple Data) C-optimization Category: An issue highlighting optimization opportunities or PRs implementing such O-AArch64 Armv8-A or later processors in AArch64 mode P-medium Medium priority regression-from-stable-to-stable Performance or correctness regression from one stable version to another. S-has-bisection Status: A bisection has been found for this issue T-compiler Relevant to the compiler team, which will review and decide on the PR/issue.
#137407 opened Feb 22, 2025 by CatsAreFluffy
8
ICE: expected SIMD field to have definite array size A-const-eval Area: Constant evaluation, covers all const contexts (static, const fn, ...) A-SIMD Area: SIMD (Single Instruction Multiple Data) C-bug Category: This is a bug. I-ICE Issue: The compiler panicked, giving an Internal Compilation Error (ICE) ❄️ T-compiler Relevant to the compiler team, which will review and decide on the PR/issue. WG-const-eval Working group: Const evaluation
#137291 opened Feb 19, 2025 by folkertdev
3
Projecting into non-power-of-two-lanes repr(simd) types does the wrong thing. A-SIMD Area: SIMD (Single Instruction Multiple Data) requires-nightly This issue requires a nightly compiler in some way.
#137108 opened Feb 16, 2025 by scottmcm
@scottmcm
2
x86 softfloat target: no way to get LLVM to make local use of the FPU or SIMD registers A-floating-point Area: Floating point numbers and arithmetic A-LLVM Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues. A-SIMD Area: SIMD (Single Instruction Multiple Data) C-bug Category: This is a bug. C-external-bug Category: issue that is caused by bugs in software beyond our control T-compiler Relevant to the compiler team, which will review and decide on the PR/issue.
#136540 opened Feb 4, 2025 by RalfJung
7
Workaround for llvm bug for f32x3 saturating fp->int opt-level=0 on aarch64 is fixed in LLVM 20 A-LLVM Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues. A-SIMD Area: SIMD (Single Instruction Multiple Data) C-cleanup Category: PRs that clean code up or issues documenting cleanup. O-AArch64 Armv8-A or later processors in AArch64 mode PG-portable-simd Project group: Portable SIMD (https://github.com/rust-lang/project-portable-simd) T-libs Relevant to the library team, which will review and decide on the PR/issue. WG-llvm Working group: LLVM backend code generation
#135982 opened Jan 24, 2025 by programmerjake
1
How should we handle dynamic vector ABIs? A-ABI Area: Concerning the application binary interface (ABI) A-SIMD Area: SIMD (Single Instruction Multiple Data) C-discussion Category: Discussion or questions that doesn't represent real issues. E-needs-design This issue needs exploration and design to see how and if we can fix/implement it O-AArch64 Armv8-A or later processors in AArch64 mode O-riscv Target: RISC-V architecture T-compiler Relevant to the compiler team, which will review and decide on the PR/issue.
#133146 opened Nov 17, 2024 by workingjubilee
How should we handle SPARC's vector ABI? A-ABI Area: Concerning the application binary interface (ABI) A-SIMD Area: SIMD (Single Instruction Multiple Data) C-discussion Category: Discussion or questions that doesn't represent real issues. E-needs-design This issue needs exploration and design to see how and if we can fix/implement it O-SPARC Target: SPARC processors T-compiler Relevant to the compiler team, which will review and decide on the PR/issue.
#133141 opened Nov 17, 2024 by workingjubilee
1
Support calling functions with SIMD vectors that couldn't be used in the caller A-ABI Area: Concerning the application binary interface (ABI) A-LLVM Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues. A-SIMD Area: SIMD (Single Instruction Multiple Data) C-feature-request Category: A feature request, i.e: not implemented / a PR. T-opsem Relevant to the opsem team WG-llvm Working group: LLVM backend code generation
#132865 opened Nov 10, 2024 by RalfJung
2
get_unchecked() is never inlined on armv7-unknown-linux-gnueabihf in functions with #[target_feature(enable = "neon")] A-codegen Area: Code generation A-LLVM Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues. A-SIMD Area: SIMD (Single Instruction Multiple Data) A-target-feature Area: Enabling/disabling target features like AVX, Neon, etc. C-bug Category: This is a bug. I-slow Issue: Problems and improvements with respect to performance of generated code. O-Arm Target: 32-bit Arm processors (armv6, armv7, thumb...), including 64-bit Arm in AArch32 state T-compiler Relevant to the compiler team, which will review and decide on the PR/issue.
#131745 opened Oct 15, 2024 by hkratz
1
s390x vector facilities support A-ABI Area: Concerning the application binary interface (ABI) A-inline-assembly Area: Inline assembly (`asm!(…)`) A-SIMD Area: SIMD (Single Instruction Multiple Data) O-SystemZ Target: SystemZ processors (s390x) T-compiler Relevant to the compiler team, which will review and decide on the PR/issue. T-libs Relevant to the library team, which will review and decide on the PR/issue.
#130869 opened Sep 26, 2024 by taiki-e
8 of 11 tasks
17
Internal SIMD layout specification is not flexible enough for SPIR-V A-align Area: alignment control (`repr(align(N))` and so on) A-repr Area: the `#[repr(stuff)]` attribute A-SIMD Area: SIMD (Single Instruction Multiple Data) PG-portable-simd Project group: Portable SIMD (https://github.com/rust-lang/project-portable-simd) T-compiler Relevant to the compiler team, which will review and decide on the PR/issue.
#130405 opened Sep 15, 2024 by fu5ha
4
When a type is #[repr(simd)], #[repr(align(N))] annotations are ignored. A-align Area: alignment control (`repr(align(N))` and so on) A-repr Area: the `#[repr(stuff)]` attribute A-SIMD Area: SIMD (Single Instruction Multiple Data) C-bug Category: This is a bug. T-compiler Relevant to the compiler team, which will review and decide on the PR/issue.
#130402 opened Sep 15, 2024 by fu5ha
1
3
Weird AVX 512 code generated with std::simd when using -Zbuild-std A-codegen Area: Code generation A-SIMD Area: SIMD (Single Instruction Multiple Data) C-bug Category: This is a bug. PG-portable-simd Project group: Portable SIMD (https://github.com/rust-lang/project-portable-simd) T-compiler Relevant to the compiler team, which will review and decide on the PR/issue.
#129293 opened Aug 20, 2024 by cvijdea-bd
1
Tracking Issue for AVX512_FP16 intrinsics A-SIMD Area: SIMD (Single Instruction Multiple Data) C-tracking-issue Category: An issue tracking the progress of sth. like the implementation of an RFC O-x86_32 Target: x86 processors, 32 bit (like i686-*) (IA-32) O-x86_64 Target: x86-64 processors (like x86_64-*) (also known as amd64 and x64) T-libs-api Relevant to the library API team, which will review and decide on the PR/issue.
#127213 opened Jul 1, 2024 by sayantn
2 tasks
2
Tracking Issue for XOP target feature A-SIMD Area: SIMD (Single Instruction Multiple Data) A-target-feature Area: Enabling/disabling target features like AVX, Neon, etc. C-tracking-issue Category: An issue tracking the progress of sth. like the implementation of an RFC O-x86_32 Target: x86 processors, 32 bit (like i686-*) (IA-32) O-x86_64 Target: x86-64 processors (like x86_64-*) (also known as amd64 and x64)
#127208 opened Jul 1, 2024 by sayantn
1 of 3 tasks
2
Wrong codegen for simd_select_bitmask on big-endian targets A-codegen Area: Code generation A-LLVM Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues. A-SIMD Area: SIMD (Single Instruction Multiple Data) C-bug Category: This is a bug. T-compiler Relevant to the compiler team, which will review and decide on the PR/issue.
#127205 opened Jul 1, 2024 by RalfJung
2
Tracking Issue for sha512_sm_x86 A-SIMD Area: SIMD (Single Instruction Multiple Data) A-target-feature Area: Enabling/disabling target features like AVX, Neon, etc. C-tracking-issue Category: An issue tracking the progress of sth. like the implementation of an RFC disposition-merge This issue / PR is in PFCP or FCP with a disposition to merge it. final-comment-period In the final comment period and will be merged soon unless new substantive objections are raised. T-libs-api Relevant to the library API team, which will review and decide on the PR/issue.
#126624 opened Jun 18, 2024 by sayantn
3 of 4 tasks
6
Tracking Issue for x86_amx_intrinsics A-SIMD Area: SIMD (Single Instruction Multiple Data) A-target-feature Area: Enabling/disabling target features like AVX, Neon, etc. C-tracking-issue Category: An issue tracking the progress of sth. like the implementation of an RFC
#126622 opened Jun 18, 2024 by sayantn
3 tasks
3
What should SIMD bitmasks look like? A-SIMD Area: SIMD (Single Instruction Multiple Data) C-discussion Category: Discussion or questions that doesn't represent real issues. PG-portable-simd Project group: Portable SIMD (https://github.com/rust-lang/project-portable-simd) T-compiler Relevant to the compiler team, which will review and decide on the PR/issue. T-opsem Relevant to the opsem team
#126217 opened Jun 10, 2024 by RalfJung
6
Add SIMD operations that use f16 and f128 A-SIMD Area: SIMD (Single Instruction Multiple Data) C-feature-request Category: A feature request, i.e: not implemented / a PR. E-help-wanted Call for participation: Help is requested to fix this issue. F-f16_and_f128 `#![feature(f16)]`, `#![feature(f128)]` T-libs Relevant to the library team, which will review and decide on the PR/issue.
#125440 opened May 23, 2024 by tgross35
12
Performance regression: rustc failed to optimize specific x86-64 SIMD intrinsics after 1.75.0 A-LLVM Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues. A-SIMD Area: SIMD (Single Instruction Multiple Data) C-bug Category: This is a bug. I-heavy Issue: Problems and improvements with respect to binary size of generated code. I-slow Issue: Problems and improvements with respect to performance of generated code. P-medium Medium priority regression-from-stable-to-stable Performance or correctness regression from one stable version to another. T-libs Relevant to the library team, which will review and decide on the PR/issue.
#124216 opened Apr 21, 2024 by Nugine
16
WASM+simd128 codegen of a.simd_eq(Simd::splat(b)).any() deteriorates as width increases A-codegen Area: Code generation A-LLVM Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues. A-SIMD Area: SIMD (Single Instruction Multiple Data) C-optimization Category: An issue highlighting optimization opportunities or PRs implementing such I-heavy Issue: Problems and improvements with respect to binary size of generated code. I-slow Issue: Problems and improvements with respect to performance of generated code. O-wasm Target: WASM (WebAssembly), http://webassembly.org/ PG-portable-simd Project group: Portable SIMD (https://github.com/rust-lang/project-portable-simd) requires-nightly This issue requires a nightly compiler in some way. S-has-mcve Status: A Minimal Complete and Verifiable Example has been found for this issue
#122623 opened Mar 17, 2024 by alion02
2
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