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# ` {arm,thumb}*-none-eabi(hf)? `
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- ## Tier 2 Target List
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+ ## Common Target Details
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+
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+ This documentation covers details that apply to a range of bare-metal targets
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+ for 32-bit Arm CPUs. The ` arm-none-eabi ` flavor of the GNU compiler toolchain is
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+ often used to assist compilation to these targets.
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+
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+ Details that apply only to only a specific target in this group are covered in
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+ their own document.
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+
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+ ### Tier 2 Target List
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- Arm A-Profile Architectures
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- ` armv7a-none-eabi `
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- * Legacy* Arm Architectures
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- None
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- ## Tier 3 Target List
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+ ### Tier 3 Target List
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- Arm A-Profile Architectures
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- ` armv7a-none-eabihf `
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- [ ` armv4t-none-eabi ` and ` thumbv4t-none-eabi ` ] ( armv4t-none-eabi.md )
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- [ ` armv5te-none-eabi ` and ` thumbv5te-none-eabi ` ] ( armv5te-none-eabi.md )
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- ## Common Target Details
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-
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- This documentation covers details that apply to a range of bare-metal targets
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- for 32-bit Arm CPUs. In addition, target specific details may be covered in
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- their own document.
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+ ## Instruction Sets
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There are two 32-bit instruction set architectures (ISAs) defined by Arm:
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@@ -43,9 +48,10 @@ There are two 32-bit instruction set architectures (ISAs) defined by Arm:
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- The [ * T32 ISA* ] [ t32-isa ] , with a mix of 16-bit and 32-bit width instructions.
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Note that this term includes both the original 16-bit width * Thumb* ISA
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introduced with the Armv4T architecture in 1994, and the later 16/32-bit sized
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- * Thumb-2* ISA introduced with the Armv6T2 architecture in 2003. Again, these
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- ISAs have been revised by subsequent revisions to the relevant Arm
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- architecture specifications.
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+ * Thumb-2* ISA introduced with the Armv6T2 architecture in 2003.
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+
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+ Again, these ISAs have been revised by subsequent revisions to the relevant Arm
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+ architecture specifications.
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There is also a 64-bit ISA with fixed-width 32-bit instructions called the * A64
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ISA* , but targets which implement that instruction set generally start with
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