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Eli Friedman
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[ARM] Prefer BIC over BFC in ARM mode.
BIC is generally faster, and it can put the output in a different register from the input. We already do this in Thumb2 mode; not sure why the equivalent fix never got applied to ARM mode. Differential Revision: https://reviews.llvm.org/D31797 llvm-svn: 299803
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-19
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8 files changed

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-19
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‎llvm/lib/Target/ARM/ARMInstrInfo.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3893,6 +3893,7 @@ def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm,
38933893
let Inst{11-0} = imm;
38943894
}
38953895

3896+
let AddedComplexity = 1 in
38963897
def : ARMPat<(and GPR:$src, mod_imm_not:$imm),
38973898
(BICri GPR:$src, mod_imm_not:$imm)>;
38983899

‎llvm/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ entry:
1919
call void @llvm.va_start(i8* %g1)
2020

2121
; CHECK: add [[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7
22-
; CHECK: bfc [[REG]], #0, #3
22+
; CHECK: bic [[REG]], [[REG]], #7
2323
%0 = va_arg i8** %g, double
2424
call void @llvm.va_end(i8* %g1)
2525

‎llvm/test/CodeGen/ARM/bfi.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -77,7 +77,7 @@ entry:
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7878
define i32 @f7(i32 %x, i32 %y) {
7979
; CHECK-LABEL: f7:
80-
; CHECK: bfi r1, r0, #4, #1
80+
; CHECK: bfi r0, r2, #4, #1
8181
%y2 = and i32 %y, 4294967040 ; 0xFFFFFF00
8282
%and = and i32 %x, 4
8383
%or = or i32 %y2, 16
@@ -88,8 +88,8 @@ define i32 @f7(i32 %x, i32 %y) {
8888

8989
define i32 @f8(i32 %x, i32 %y) {
9090
; CHECK-LABEL: f8:
91-
; CHECK: bfi r1, r0, #4, #1
92-
; CHECK: bfi r1, r0, #5, #1
91+
; CHECK: bfi r0, r2, #4, #1
92+
; CHECK: bfi r0, r2, #5, #1
9393
%y2 = and i32 %y, 4294967040 ; 0xFFFFFF00
9494
%and = and i32 %x, 4
9595
%or = or i32 %y2, 48
@@ -111,7 +111,7 @@ define i32 @f9(i32 %x, i32 %y) {
111111

112112
define i32 @f10(i32 %x, i32 %y) {
113113
; CHECK-LABEL: f10:
114-
; CHECK: bfi r1, r0, #4, #2
114+
; CHECK: bfi r0, r2, #4, #2
115115
%y2 = and i32 %y, 4294967040 ; 0xFFFFFF00
116116
%and = and i32 %x, 4
117117
%or = or i32 %y2, 32
@@ -128,7 +128,7 @@ define i32 @f10(i32 %x, i32 %y) {
128128

129129
define i32 @f11(i32 %x, i32 %y) {
130130
; CHECK-LABEL: f11:
131-
; CHECK: bfi r1, r0, #4, #3
131+
; CHECK: bfi r0, r2, #4, #3
132132
%y2 = and i32 %y, 4294967040 ; 0xFFFFFF00
133133
%and = and i32 %x, 4
134134
%or = or i32 %y2, 32
@@ -150,7 +150,7 @@ define i32 @f11(i32 %x, i32 %y) {
150150

151151
define i32 @f12(i32 %x, i32 %y) {
152152
; CHECK-LABEL: f12:
153-
; CHECK: bfi r1, r0, #4, #1
153+
; CHECK: bfi r0, r2, #4, #1
154154
%y2 = and i32 %y, 4294967040 ; 0xFFFFFF00
155155
%and = and i32 %x, 4
156156
%or = or i32 %y2, 16

‎llvm/test/CodeGen/ARM/bic.ll

Lines changed: 10 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,17 +1,24 @@
11
; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
22

33
define i32 @f1(i32 %a, i32 %b) {
4+
; CHECK-LABEL: f1:
5+
; CHECK: bic r0, r0, r1
46
%tmp = xor i32 %b, 4294967295
57
%tmp1 = and i32 %a, %tmp
68
ret i32 %tmp1
79
}
810

9-
; CHECK: bic r0, r0, r1
10-
1111
define i32 @f2(i32 %a, i32 %b) {
12+
; CHECK-LABEL: f2:
13+
; CHECK: bic r0, r0, r1
1214
%tmp = xor i32 %b, 4294967295
1315
%tmp1 = and i32 %tmp, %a
1416
ret i32 %tmp1
1517
}
1618

17-
; CHECK: bic r0, r0, r1
19+
define i32 @f3(i32 %a) {
20+
; CHECK-LABEL: f3:
21+
; CHECK: bic r0, r0, #255
22+
%tmp = and i32 %a, -256
23+
ret i32 %tmp
24+
}

‎llvm/test/CodeGen/ARM/fp16-promote.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -597,7 +597,7 @@ define void @test_fma(half* %p, half* %q, half* %r) #0 {
597597
; CHECK-FP16: vcvtb.f16.f32
598598
; CHECK-LIBCALL-LABEL: test_fabs:
599599
; CHECK-LIBCALL: bl __aeabi_h2f
600-
; CHECK-LIBCALL: bfc
600+
; CHECK-LIBCALL: bic
601601
; CHECK-LIBCALL: bl __aeabi_f2h
602602
define void @test_fabs(half* %p) {
603603
%a = load half, half* %p, align 2
@@ -687,7 +687,7 @@ define void @test_maxnan(half* %p) #0 {
687687
; CHECK-LIBCALL: bl __aeabi_h2f
688688
; CHECK-LIBCALL: bl __aeabi_h2f
689689
; CHECK-VFP-LIBCALL: vbsl
690-
; CHECK-NOVFP: bfc
690+
; CHECK-NOVFP: bic
691691
; CHECK-NOVFP: and
692692
; CHECK-NOVFP: orr
693693
; CHECK-LIBCALL: bl __aeabi_f2h

‎llvm/test/CodeGen/ARM/fpcmp-opt.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,7 @@ entry:
3535
; CHECK-NOT: vldr
3636
; CHECK: ldrd [[REG1:(r[0-9]+)]], [[REG2:(r[0-9]+)]], [r0]
3737
; CHECK-NOT: b LBB
38-
; CHECK: bfc [[REG2]], #31, #1
38+
; CHECK: bic [[REG2]], [[REG2]], #-2147483648
3939
; CHECK: cmp [[REG1]], #0
4040
; CHECK: cmpeq [[REG2]], #0
4141
; CHECK-NOT: vcmp.f32

‎llvm/test/CodeGen/ARM/softfp-fabs-fneg.ll

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -14,8 +14,7 @@ define double @f(double %a) {
1414

1515
define float @g(float %a) {
1616
; CHECK-LABEL: g:
17-
; CHECK-THUMB: bic r0, r0, #-2147483648
18-
; CHECK-ARM: bfc r0, #31, #1
17+
; CHECK: bic r0, r0, #-2147483648
1918
; CHECK-NEXT: bx lr
2019
%x = call float @llvm.fabs.f32(float %a) readnone
2120
ret float %x

‎llvm/test/CodeGen/ARM/va_arg.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -4,8 +4,8 @@
44
; CHECK-LABEL: test1:
55
; CHECK-NOT: bfc
66
; CHECK: add [[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7
7-
; CHECK: bfc [[REG]], #0, #3
8-
; CHECK-NOT: bfc
7+
; CHECK: bic {{(r[0-9]+)|(lr)}}, [[REG]], #7
8+
; CHECK-NOT: bic
99

1010
define i64 @test1(i32 %i, ...) nounwind optsize {
1111
entry:
@@ -20,8 +20,8 @@ entry:
2020
; CHECK-LABEL: test2:
2121
; CHECK-NOT: bfc
2222
; CHECK: add [[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7
23-
; CHECK: bfc [[REG]], #0, #3
24-
; CHECK-NOT: bfc
23+
; CHECK: bic {{(r[0-9]+)|(lr)}}, [[REG]], #7
24+
; CHECK-NOT: bic
2525
; CHECK: bx lr
2626

2727
define double @test2(i32 %a, i32* %b, ...) nounwind optsize {

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