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Narrow or widen the vector element without changing the vector size
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src/etc/platform-intrinsics/generator.py

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@
1919
SPEC = re.compile(
2020
r'^(?:(?P<void>V)|(?P<id>[iusfIUSF])(?:\((?P<start>\d+)-(?P<end>\d+)\)|'
2121
r'(?P<width>\d+)(:?/(?P<llvm_width>\d+))?)'
22-
r'|(?P<reference>\d+))(?P<index>\.\d+)?(?P<modifiers>[vShdnwusfDMC]*)(?P<force_width>x\d+)?'
22+
r'|(?P<reference>\d+))(?P<index>\.\d+)?(?P<modifiers>[vShdnwusfDMCNW]*)(?P<force_width>x\d+)?'
2323
r'(?:(?P<pointer>Pm|Pc)(?P<llvm_pointer>/.*)?|(?P<bitcast>->.*))?$'
2424
)
2525

@@ -246,6 +246,12 @@ def modify(self, spec, width, previous):
246246
return Vector(self._elem, self._length // 2)
247247
elif spec == 'd':
248248
return Vector(self._elem, self._length * 2)
249+
elif spec == 'N':
250+
elem = self._elem.__class__(self._elem.bitwidth() // 2)
251+
return Vector(elem, self._length * 2)
252+
elif spec == 'W':
253+
elem = self._elem.__class__(self._elem.bitwidth() * 2)
254+
return Vector(elem, self._length // 2)
249255
elif spec.startswith('x'):
250256
new_bitwidth = int(spec[1:])
251257
return Vector(self._elem, new_bitwidth // self._elem.bitwidth())
@@ -714,6 +720,8 @@ def parse_args():
714720
- 'd': double the length of the vector (u32x2 -> u32x4)
715721
- 'n': narrow the element of the vector (u32x4 -> u16x4)
716722
- 'w': widen the element of the vector (u16x4 -> u32x4)
723+
- 'N': half the length of the vector element (u32x4 -> u16x8)
724+
- 'W': double the length of the vector element (u16x8 -> u32x4)
717725
- 'u': force a number (vector or scalar) to be unsigned int (f32x4 -> u32x4)
718726
- 's': force a number (vector or scalar) to be signed int (u32x4 -> i32x4)
719727
- 'f': force a number (vector or scalar) to be float (u32x4 -> f32x4)

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