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Merging r323369 and r323371:
------------------------------------------------------------------------ r323369 | aemerson | 2018-01-24 20:59:29 +0100 (Wed, 24 Jan 2018) | 4 lines [GlobalISel] Don't fall back to FastISel. Apparently checking the pass structure isn't enough to ensure that we don't fall back to FastISel, as it's set up as part of the SelectionDAGISel. ------------------------------------------------------------------------ ------------------------------------------------------------------------ r323371 | aemerson | 2018-01-24 21:35:37 +0100 (Wed, 24 Jan 2018) | 12 lines [AArch64][GlobalISel] Fall back during AArch64 isel if we have a volatile load. The tablegen imported patterns for sext(load(a)) don't check for single uses of the load or delete the original after matching. As a result two loads are left in the generated code. This particular issue will be fixed by adding support for a G_SEXTLOAD opcode in future. There are however other potential issues around this that wouldn't be fixed by a G_SEXTLOAD, so until we have a proper solution we don't try to handle volatile loads at all in the AArch64 selector. Fixes/works around PR36018. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@323434 91177308-0d34-0410-b5e6-96231b3b80d8
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lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Lines changed: 3 additions & 1 deletion
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@@ -1380,8 +1380,10 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
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FastISelFailed = false;
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// Initialize the Fast-ISel state, if needed.
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FastISel *FastIS = nullptr;
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if (TM.Options.EnableFastISel)
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if (TM.Options.EnableFastISel) {
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DEBUG(dbgs() << "Enabling fast-isel\n");
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FastIS = TLI->createFastISel(*FuncInfo, LibInfo);
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}
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setupSwiftErrorVals(Fn, TLI, FuncInfo);
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lib/CodeGen/TargetPassConfig.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -717,6 +717,8 @@ bool TargetPassConfig::addCoreISelPasses() {
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if (EnableGlobalISel == cl::BOU_TRUE ||
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(EnableGlobalISel == cl::BOU_UNSET && isGlobalISelEnabled() &&
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EnableFastISelOption != cl::BOU_TRUE)) {
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TM->setFastISel(false);
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if (addIRTranslator())
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return true;
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lib/Target/AArch64/AArch64InstructionSelector.cpp

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@@ -929,6 +929,12 @@ bool AArch64InstructionSelector::select(MachineInstr &I,
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return false;
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}
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// FIXME: PR36018: Volatile loads in some cases are incorrectly selected by
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// folding with an extend. Until we have a G_SEXTLOAD solution bail out if
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// we hit one.
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if (Opcode == TargetOpcode::G_LOAD && MemOp.isVolatile())
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return false;
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const unsigned PtrReg = I.getOperand(1).getReg();
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#ifndef NDEBUG
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const RegisterBank &PtrRB = *RBI.getRegBank(PtrReg, MRI, TRI);
Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
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; RUN: llc -mtriple=aarch64_be-- %s -o /dev/null -debug-only=isel -O0 2>&1 | FileCheck %s
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; This test uses big endian in order to force an abort since it's not currently supported for GISel.
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; The purpose is to check that we don't fall back to FastISel. Checking the pass structure is insufficient
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; because the FastISel is set up in the SelectionDAGISel, so it doesn't appear on the pass structure.
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; CHECK-NOT: Enabling fast-ise
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define void @empty() {
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ret void
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}
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@@ -0,0 +1,14 @@
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; RUN: llc -O0 -mtriple=aarch64-apple-ios -o - %s | FileCheck %s
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@g = global i16 0, align 2
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declare void @bar(i32)
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; Check that only one load is generated. We fall back to
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define hidden void @foo() {
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; CHECK-NOT: ldrh
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; CHECK: ldrsh
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%1 = load volatile i16, i16* @g, align 2
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%2 = sext i16 %1 to i32
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call void @bar(i32 %2)
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ret void
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}

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