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[X86][AArch64] Add additional extract_lowbits test
Check that vreg_width-1 mask is only removed for shifts Differential Revision: https://reviews.llvm.org/D155734
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-246
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2 files changed

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-246
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‎llvm/test/CodeGen/AArch64/extract-lowbits.ll

Lines changed: 54 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@
2121
define i32 @bzhi32_a0(i32 %val, i32 %numlowbits) nounwind {
2222
; CHECK-LABEL: bzhi32_a0:
2323
; CHECK: // %bb.0:
24-
; CHECK-NEXT: mov w8, #1
24+
; CHECK-NEXT: mov w8, #1 // =0x1
2525
; CHECK-NEXT: lsl w8, w8, w1
2626
; CHECK-NEXT: sub w8, w8, #1
2727
; CHECK-NEXT: and w0, w8, w0
@@ -35,7 +35,7 @@ define i32 @bzhi32_a0(i32 %val, i32 %numlowbits) nounwind {
3535
define i32 @bzhi32_a1_indexzext(i32 %val, i8 zeroext %numlowbits) nounwind {
3636
; CHECK-LABEL: bzhi32_a1_indexzext:
3737
; CHECK: // %bb.0:
38-
; CHECK-NEXT: mov w8, #1
38+
; CHECK-NEXT: mov w8, #1 // =0x1
3939
; CHECK-NEXT: lsl w8, w8, w1
4040
; CHECK-NEXT: sub w8, w8, #1
4141
; CHECK-NEXT: and w0, w8, w0
@@ -50,7 +50,7 @@ define i32 @bzhi32_a1_indexzext(i32 %val, i8 zeroext %numlowbits) nounwind {
5050
define i32 @bzhi32_a2_load(ptr %w, i32 %numlowbits) nounwind {
5151
; CHECK-LABEL: bzhi32_a2_load:
5252
; CHECK: // %bb.0:
53-
; CHECK-NEXT: mov w8, #1
53+
; CHECK-NEXT: mov w8, #1 // =0x1
5454
; CHECK-NEXT: ldr w9, [x0]
5555
; CHECK-NEXT: lsl w8, w8, w1
5656
; CHECK-NEXT: sub w8, w8, #1
@@ -66,7 +66,7 @@ define i32 @bzhi32_a2_load(ptr %w, i32 %numlowbits) nounwind {
6666
define i32 @bzhi32_a3_load_indexzext(ptr %w, i8 zeroext %numlowbits) nounwind {
6767
; CHECK-LABEL: bzhi32_a3_load_indexzext:
6868
; CHECK: // %bb.0:
69-
; CHECK-NEXT: mov w8, #1
69+
; CHECK-NEXT: mov w8, #1 // =0x1
7070
; CHECK-NEXT: ldr w9, [x0]
7171
; CHECK-NEXT: lsl w8, w8, w1
7272
; CHECK-NEXT: sub w8, w8, #1
@@ -83,7 +83,7 @@ define i32 @bzhi32_a3_load_indexzext(ptr %w, i8 zeroext %numlowbits) nounwind {
8383
define i32 @bzhi32_a4_commutative(i32 %val, i32 %numlowbits) nounwind {
8484
; CHECK-LABEL: bzhi32_a4_commutative:
8585
; CHECK: // %bb.0:
86-
; CHECK-NEXT: mov w8, #1
86+
; CHECK-NEXT: mov w8, #1 // =0x1
8787
; CHECK-NEXT: lsl w8, w8, w1
8888
; CHECK-NEXT: sub w8, w8, #1
8989
; CHECK-NEXT: and w0, w0, w8
@@ -99,7 +99,7 @@ define i32 @bzhi32_a4_commutative(i32 %val, i32 %numlowbits) nounwind {
9999
define i64 @bzhi64_a0(i64 %val, i64 %numlowbits) nounwind {
100100
; CHECK-LABEL: bzhi64_a0:
101101
; CHECK: // %bb.0:
102-
; CHECK-NEXT: mov w8, #1
102+
; CHECK-NEXT: mov w8, #1 // =0x1
103103
; CHECK-NEXT: lsl x8, x8, x1
104104
; CHECK-NEXT: sub x8, x8, #1
105105
; CHECK-NEXT: and x0, x8, x0
@@ -110,10 +110,26 @@ define i64 @bzhi64_a0(i64 %val, i64 %numlowbits) nounwind {
110110
ret i64 %masked
111111
}
112112

113+
; Check that we don't throw away the vreg_width-1 mask if not using shifts
114+
define i64 @bzhi64_a0_masked(i64 %val, i64 %numlowbits) nounwind {
115+
; CHECK-LABEL: bzhi64_a0_masked:
116+
; CHECK: // %bb.0:
117+
; CHECK-NEXT: mov w8, #1 // =0x1
118+
; CHECK-NEXT: lsl x8, x8, x1
119+
; CHECK-NEXT: sub x8, x8, #1
120+
; CHECK-NEXT: and x0, x8, x0
121+
; CHECK-NEXT: ret
122+
%numlowbits.masked = and i64 %numlowbits, 63
123+
%onebit = shl i64 1, %numlowbits.masked
124+
%mask = add nsw i64 %onebit, -1
125+
%masked = and i64 %mask, %val
126+
ret i64 %masked
127+
}
128+
113129
define i64 @bzhi64_a1_indexzext(i64 %val, i8 zeroext %numlowbits) nounwind {
114130
; CHECK-LABEL: bzhi64_a1_indexzext:
115131
; CHECK: // %bb.0:
116-
; CHECK-NEXT: mov w8, #1
132+
; CHECK-NEXT: mov w8, #1 // =0x1
117133
; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
118134
; CHECK-NEXT: lsl x8, x8, x1
119135
; CHECK-NEXT: sub x8, x8, #1
@@ -129,7 +145,7 @@ define i64 @bzhi64_a1_indexzext(i64 %val, i8 zeroext %numlowbits) nounwind {
129145
define i64 @bzhi64_a2_load(ptr %w, i64 %numlowbits) nounwind {
130146
; CHECK-LABEL: bzhi64_a2_load:
131147
; CHECK: // %bb.0:
132-
; CHECK-NEXT: mov w8, #1
148+
; CHECK-NEXT: mov w8, #1 // =0x1
133149
; CHECK-NEXT: ldr x9, [x0]
134150
; CHECK-NEXT: lsl x8, x8, x1
135151
; CHECK-NEXT: sub x8, x8, #1
@@ -145,7 +161,7 @@ define i64 @bzhi64_a2_load(ptr %w, i64 %numlowbits) nounwind {
145161
define i64 @bzhi64_a3_load_indexzext(ptr %w, i8 zeroext %numlowbits) nounwind {
146162
; CHECK-LABEL: bzhi64_a3_load_indexzext:
147163
; CHECK: // %bb.0:
148-
; CHECK-NEXT: mov w8, #1
164+
; CHECK-NEXT: mov w8, #1 // =0x1
149165
; CHECK-NEXT: ldr x9, [x0]
150166
; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
151167
; CHECK-NEXT: lsl x8, x8, x1
@@ -163,7 +179,7 @@ define i64 @bzhi64_a3_load_indexzext(ptr %w, i8 zeroext %numlowbits) nounwind {
163179
define i64 @bzhi64_a4_commutative(i64 %val, i64 %numlowbits) nounwind {
164180
; CHECK-LABEL: bzhi64_a4_commutative:
165181
; CHECK: // %bb.0:
166-
; CHECK-NEXT: mov w8, #1
182+
; CHECK-NEXT: mov w8, #1 // =0x1
167183
; CHECK-NEXT: lsl x8, x8, x1
168184
; CHECK-NEXT: sub x8, x8, #1
169185
; CHECK-NEXT: and x0, x0, x8
@@ -181,7 +197,7 @@ define i64 @bzhi64_a4_commutative(i64 %val, i64 %numlowbits) nounwind {
181197
define i32 @bzhi32_b0(i32 %val, i32 %numlowbits) nounwind {
182198
; CHECK-LABEL: bzhi32_b0:
183199
; CHECK: // %bb.0:
184-
; CHECK-NEXT: mov w8, #-1
200+
; CHECK-NEXT: mov w8, #-1 // =0xffffffff
185201
; CHECK-NEXT: lsl w8, w8, w1
186202
; CHECK-NEXT: bic w0, w0, w8
187203
; CHECK-NEXT: ret
@@ -194,7 +210,7 @@ define i32 @bzhi32_b0(i32 %val, i32 %numlowbits) nounwind {
194210
define i32 @bzhi32_b1_indexzext(i32 %val, i8 zeroext %numlowbits) nounwind {
195211
; CHECK-LABEL: bzhi32_b1_indexzext:
196212
; CHECK: // %bb.0:
197-
; CHECK-NEXT: mov w8, #-1
213+
; CHECK-NEXT: mov w8, #-1 // =0xffffffff
198214
; CHECK-NEXT: lsl w8, w8, w1
199215
; CHECK-NEXT: bic w0, w0, w8
200216
; CHECK-NEXT: ret
@@ -209,7 +225,7 @@ define i32 @bzhi32_b2_load(ptr %w, i32 %numlowbits) nounwind {
209225
; CHECK-LABEL: bzhi32_b2_load:
210226
; CHECK: // %bb.0:
211227
; CHECK-NEXT: ldr w8, [x0]
212-
; CHECK-NEXT: mov w9, #-1
228+
; CHECK-NEXT: mov w9, #-1 // =0xffffffff
213229
; CHECK-NEXT: lsl w9, w9, w1
214230
; CHECK-NEXT: bic w0, w8, w9
215231
; CHECK-NEXT: ret
@@ -224,7 +240,7 @@ define i32 @bzhi32_b3_load_indexzext(ptr %w, i8 zeroext %numlowbits) nounwind {
224240
; CHECK-LABEL: bzhi32_b3_load_indexzext:
225241
; CHECK: // %bb.0:
226242
; CHECK-NEXT: ldr w8, [x0]
227-
; CHECK-NEXT: mov w9, #-1
243+
; CHECK-NEXT: mov w9, #-1 // =0xffffffff
228244
; CHECK-NEXT: lsl w9, w9, w1
229245
; CHECK-NEXT: bic w0, w8, w9
230246
; CHECK-NEXT: ret
@@ -239,7 +255,7 @@ define i32 @bzhi32_b3_load_indexzext(ptr %w, i8 zeroext %numlowbits) nounwind {
239255
define i32 @bzhi32_b4_commutative(i32 %val, i32 %numlowbits) nounwind {
240256
; CHECK-LABEL: bzhi32_b4_commutative:
241257
; CHECK: // %bb.0:
242-
; CHECK-NEXT: mov w8, #-1
258+
; CHECK-NEXT: mov w8, #-1 // =0xffffffff
243259
; CHECK-NEXT: lsl w8, w8, w1
244260
; CHECK-NEXT: bic w0, w0, w8
245261
; CHECK-NEXT: ret
@@ -254,7 +270,7 @@ define i32 @bzhi32_b4_commutative(i32 %val, i32 %numlowbits) nounwind {
254270
define i64 @bzhi64_b0(i64 %val, i64 %numlowbits) nounwind {
255271
; CHECK-LABEL: bzhi64_b0:
256272
; CHECK: // %bb.0:
257-
; CHECK-NEXT: mov x8, #-1
273+
; CHECK-NEXT: mov x8, #-1 // =0xffffffffffffffff
258274
; CHECK-NEXT: lsl x8, x8, x1
259275
; CHECK-NEXT: bic x0, x0, x8
260276
; CHECK-NEXT: ret
@@ -267,7 +283,7 @@ define i64 @bzhi64_b0(i64 %val, i64 %numlowbits) nounwind {
267283
define i64 @bzhi64_b1_indexzext(i64 %val, i8 zeroext %numlowbits) nounwind {
268284
; CHECK-LABEL: bzhi64_b1_indexzext:
269285
; CHECK: // %bb.0:
270-
; CHECK-NEXT: mov x8, #-1
286+
; CHECK-NEXT: mov x8, #-1 // =0xffffffffffffffff
271287
; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
272288
; CHECK-NEXT: lsl x8, x8, x1
273289
; CHECK-NEXT: bic x0, x0, x8
@@ -283,7 +299,7 @@ define i64 @bzhi64_b2_load(ptr %w, i64 %numlowbits) nounwind {
283299
; CHECK-LABEL: bzhi64_b2_load:
284300
; CHECK: // %bb.0:
285301
; CHECK-NEXT: ldr x8, [x0]
286-
; CHECK-NEXT: mov x9, #-1
302+
; CHECK-NEXT: mov x9, #-1 // =0xffffffffffffffff
287303
; CHECK-NEXT: lsl x9, x9, x1
288304
; CHECK-NEXT: bic x0, x8, x9
289305
; CHECK-NEXT: ret
@@ -298,7 +314,7 @@ define i64 @bzhi64_b3_load_indexzext(ptr %w, i8 zeroext %numlowbits) nounwind {
298314
; CHECK-LABEL: bzhi64_b3_load_indexzext:
299315
; CHECK: // %bb.0:
300316
; CHECK-NEXT: ldr x8, [x0]
301-
; CHECK-NEXT: mov x9, #-1
317+
; CHECK-NEXT: mov x9, #-1 // =0xffffffffffffffff
302318
; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
303319
; CHECK-NEXT: lsl x9, x9, x1
304320
; CHECK-NEXT: bic x0, x8, x9
@@ -314,7 +330,7 @@ define i64 @bzhi64_b3_load_indexzext(ptr %w, i8 zeroext %numlowbits) nounwind {
314330
define i64 @bzhi64_b4_commutative(i64 %val, i64 %numlowbits) nounwind {
315331
; CHECK-LABEL: bzhi64_b4_commutative:
316332
; CHECK: // %bb.0:
317-
; CHECK-NEXT: mov x8, #-1
333+
; CHECK-NEXT: mov x8, #-1 // =0xffffffffffffffff
318334
; CHECK-NEXT: lsl x8, x8, x1
319335
; CHECK-NEXT: bic x0, x0, x8
320336
; CHECK-NEXT: ret
@@ -332,7 +348,7 @@ define i32 @bzhi32_c0(i32 %val, i32 %numlowbits) nounwind {
332348
; CHECK-LABEL: bzhi32_c0:
333349
; CHECK: // %bb.0:
334350
; CHECK-NEXT: neg w8, w1
335-
; CHECK-NEXT: mov w9, #-1
351+
; CHECK-NEXT: mov w9, #-1 // =0xffffffff
336352
; CHECK-NEXT: lsr w8, w9, w8
337353
; CHECK-NEXT: and w0, w8, w0
338354
; CHECK-NEXT: ret
@@ -345,8 +361,8 @@ define i32 @bzhi32_c0(i32 %val, i32 %numlowbits) nounwind {
345361
define i32 @bzhi32_c1_indexzext(i32 %val, i8 %numlowbits) nounwind {
346362
; CHECK-LABEL: bzhi32_c1_indexzext:
347363
; CHECK: // %bb.0:
348-
; CHECK-NEXT: mov w8, #32
349-
; CHECK-NEXT: mov w9, #-1
364+
; CHECK-NEXT: mov w8, #32 // =0x20
365+
; CHECK-NEXT: mov w9, #-1 // =0xffffffff
350366
; CHECK-NEXT: sub w8, w8, w1
351367
; CHECK-NEXT: lsr w8, w9, w8
352368
; CHECK-NEXT: and w0, w8, w0
@@ -363,7 +379,7 @@ define i32 @bzhi32_c2_load(ptr %w, i32 %numlowbits) nounwind {
363379
; CHECK: // %bb.0:
364380
; CHECK-NEXT: neg w8, w1
365381
; CHECK-NEXT: ldr w9, [x0]
366-
; CHECK-NEXT: mov w10, #-1
382+
; CHECK-NEXT: mov w10, #-1 // =0xffffffff
367383
; CHECK-NEXT: lsr w8, w10, w8
368384
; CHECK-NEXT: and w0, w8, w9
369385
; CHECK-NEXT: ret
@@ -377,10 +393,10 @@ define i32 @bzhi32_c2_load(ptr %w, i32 %numlowbits) nounwind {
377393
define i32 @bzhi32_c3_load_indexzext(ptr %w, i8 %numlowbits) nounwind {
378394
; CHECK-LABEL: bzhi32_c3_load_indexzext:
379395
; CHECK: // %bb.0:
380-
; CHECK-NEXT: mov w8, #32
396+
; CHECK-NEXT: mov w8, #32 // =0x20
381397
; CHECK-NEXT: ldr w9, [x0]
382398
; CHECK-NEXT: sub w8, w8, w1
383-
; CHECK-NEXT: mov w10, #-1
399+
; CHECK-NEXT: mov w10, #-1 // =0xffffffff
384400
; CHECK-NEXT: lsr w8, w10, w8
385401
; CHECK-NEXT: and w0, w8, w9
386402
; CHECK-NEXT: ret
@@ -396,7 +412,7 @@ define i32 @bzhi32_c4_commutative(i32 %val, i32 %numlowbits) nounwind {
396412
; CHECK-LABEL: bzhi32_c4_commutative:
397413
; CHECK: // %bb.0:
398414
; CHECK-NEXT: neg w8, w1
399-
; CHECK-NEXT: mov w9, #-1
415+
; CHECK-NEXT: mov w9, #-1 // =0xffffffff
400416
; CHECK-NEXT: lsr w8, w9, w8
401417
; CHECK-NEXT: and w0, w0, w8
402418
; CHECK-NEXT: ret
@@ -412,7 +428,7 @@ define i64 @bzhi64_c0(i64 %val, i64 %numlowbits) nounwind {
412428
; CHECK-LABEL: bzhi64_c0:
413429
; CHECK: // %bb.0:
414430
; CHECK-NEXT: neg x8, x1
415-
; CHECK-NEXT: mov x9, #-1
431+
; CHECK-NEXT: mov x9, #-1 // =0xffffffffffffffff
416432
; CHECK-NEXT: lsr x8, x9, x8
417433
; CHECK-NEXT: and x0, x8, x0
418434
; CHECK-NEXT: ret
@@ -425,8 +441,8 @@ define i64 @bzhi64_c0(i64 %val, i64 %numlowbits) nounwind {
425441
define i64 @bzhi64_c1_indexzext(i64 %val, i8 %numlowbits) nounwind {
426442
; CHECK-LABEL: bzhi64_c1_indexzext:
427443
; CHECK: // %bb.0:
428-
; CHECK-NEXT: mov w8, #64
429-
; CHECK-NEXT: mov x9, #-1
444+
; CHECK-NEXT: mov w8, #64 // =0x40
445+
; CHECK-NEXT: mov x9, #-1 // =0xffffffffffffffff
430446
; CHECK-NEXT: sub w8, w8, w1
431447
; CHECK-NEXT: lsr x8, x9, x8
432448
; CHECK-NEXT: and x0, x8, x0
@@ -443,7 +459,7 @@ define i64 @bzhi64_c2_load(ptr %w, i64 %numlowbits) nounwind {
443459
; CHECK: // %bb.0:
444460
; CHECK-NEXT: neg x8, x1
445461
; CHECK-NEXT: ldr x9, [x0]
446-
; CHECK-NEXT: mov x10, #-1
462+
; CHECK-NEXT: mov x10, #-1 // =0xffffffffffffffff
447463
; CHECK-NEXT: lsr x8, x10, x8
448464
; CHECK-NEXT: and x0, x8, x9
449465
; CHECK-NEXT: ret
@@ -457,10 +473,10 @@ define i64 @bzhi64_c2_load(ptr %w, i64 %numlowbits) nounwind {
457473
define i64 @bzhi64_c3_load_indexzext(ptr %w, i8 %numlowbits) nounwind {
458474
; CHECK-LABEL: bzhi64_c3_load_indexzext:
459475
; CHECK: // %bb.0:
460-
; CHECK-NEXT: mov w8, #64
476+
; CHECK-NEXT: mov w8, #64 // =0x40
461477
; CHECK-NEXT: ldr x9, [x0]
462478
; CHECK-NEXT: sub w8, w8, w1
463-
; CHECK-NEXT: mov x10, #-1
479+
; CHECK-NEXT: mov x10, #-1 // =0xffffffffffffffff
464480
; CHECK-NEXT: lsr x8, x10, x8
465481
; CHECK-NEXT: and x0, x8, x9
466482
; CHECK-NEXT: ret
@@ -476,7 +492,7 @@ define i64 @bzhi64_c4_commutative(i64 %val, i64 %numlowbits) nounwind {
476492
; CHECK-LABEL: bzhi64_c4_commutative:
477493
; CHECK: // %bb.0:
478494
; CHECK-NEXT: neg x8, x1
479-
; CHECK-NEXT: mov x9, #-1
495+
; CHECK-NEXT: mov x9, #-1 // =0xffffffffffffffff
480496
; CHECK-NEXT: lsr x8, x9, x8
481497
; CHECK-NEXT: and x0, x0, x8
482498
; CHECK-NEXT: ret
@@ -506,7 +522,7 @@ define i32 @bzhi32_d0(i32 %val, i32 %numlowbits) nounwind {
506522
define i32 @bzhi32_d1_indexzext(i32 %val, i8 %numlowbits) nounwind {
507523
; CHECK-LABEL: bzhi32_d1_indexzext:
508524
; CHECK: // %bb.0:
509-
; CHECK-NEXT: mov w8, #32
525+
; CHECK-NEXT: mov w8, #32 // =0x20
510526
; CHECK-NEXT: sub w8, w8, w1
511527
; CHECK-NEXT: lsl w9, w0, w8
512528
; CHECK-NEXT: lsr w0, w9, w8
@@ -536,7 +552,7 @@ define i32 @bzhi32_d2_load(ptr %w, i32 %numlowbits) nounwind {
536552
define i32 @bzhi32_d3_load_indexzext(ptr %w, i8 %numlowbits) nounwind {
537553
; CHECK-LABEL: bzhi32_d3_load_indexzext:
538554
; CHECK: // %bb.0:
539-
; CHECK-NEXT: mov w8, #32
555+
; CHECK-NEXT: mov w8, #32 // =0x20
540556
; CHECK-NEXT: ldr w9, [x0]
541557
; CHECK-NEXT: sub w8, w8, w1
542558
; CHECK-NEXT: lsl w9, w9, w8
@@ -568,7 +584,7 @@ define i64 @bzhi64_d0(i64 %val, i64 %numlowbits) nounwind {
568584
define i64 @bzhi64_d1_indexzext(i64 %val, i8 %numlowbits) nounwind {
569585
; CHECK-LABEL: bzhi64_d1_indexzext:
570586
; CHECK: // %bb.0:
571-
; CHECK-NEXT: mov w8, #64
587+
; CHECK-NEXT: mov w8, #64 // =0x40
572588
; CHECK-NEXT: sub w8, w8, w1
573589
; CHECK-NEXT: lsl x9, x0, x8
574590
; CHECK-NEXT: lsr x0, x9, x8
@@ -598,7 +614,7 @@ define i64 @bzhi64_d2_load(ptr %w, i64 %numlowbits) nounwind {
598614
define i64 @bzhi64_d3_load_indexzext(ptr %w, i8 %numlowbits) nounwind {
599615
; CHECK-LABEL: bzhi64_d3_load_indexzext:
600616
; CHECK: // %bb.0:
601-
; CHECK-NEXT: mov w8, #64
617+
; CHECK-NEXT: mov w8, #64 // =0x40
602618
; CHECK-NEXT: ldr x9, [x0]
603619
; CHECK-NEXT: sub w8, w8, w1
604620
; CHECK-NEXT: lsl x9, x9, x8

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