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[PowerPC] Support constrained vector fp/int conversion
This patch makes these operations legal, and add necessary codegen patterns. There's still some issue similar to D77033 for conversion from v1i128 type. But normal type tests synced in vector-constrained-fp-intrinsic are passed successfully. Reviewed By: uweigand Differential Revision: https://reviews.llvm.org/D83654
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+2947
-486
lines changed

4 files changed

+2947
-486
lines changed

‎llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Lines changed: 49 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -824,6 +824,10 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
824824
setOperationAction(ISD::SELECT, MVT::v4i32,
825825
Subtarget.useCRBits() ? Legal : Expand);
826826
setOperationAction(ISD::STORE , MVT::v4i32, Legal);
827+
setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v4i32, Legal);
828+
setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v4i32, Legal);
829+
setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i32, Legal);
830+
setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i32, Legal);
827831
setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
828832
setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
829833
setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
@@ -1002,6 +1006,10 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
10021006

10031007
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
10041008

1009+
setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i64, Legal);
1010+
setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i64, Legal);
1011+
setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v2i64, Legal);
1012+
setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v2i64, Legal);
10051013
setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
10061014
setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
10071015
setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
@@ -1010,6 +1018,14 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
10101018
// Custom handling for partial vectors of integers converted to
10111019
// floating point. We already have optimal handling for v2i32 through
10121020
// the DAG combine, so those aren't necessary.
1021+
setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i8, Custom);
1022+
setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i8, Custom);
1023+
setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i16, Custom);
1024+
setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i16, Custom);
1025+
setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i8, Custom);
1026+
setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i8, Custom);
1027+
setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i16, Custom);
1028+
setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i16, Custom);
10131029
setOperationAction(ISD::UINT_TO_FP, MVT::v2i8, Custom);
10141030
setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
10151031
setOperationAction(ISD::UINT_TO_FP, MVT::v2i16, Custom);
@@ -8346,17 +8362,19 @@ static SDValue widenVec(SelectionDAG &DAG, SDValue Vec, const SDLoc &dl) {
83468362

83478363
SDValue PPCTargetLowering::LowerINT_TO_FPVector(SDValue Op, SelectionDAG &DAG,
83488364
const SDLoc &dl) const {
8349-
8365+
bool IsStrict = Op->isStrictFPOpcode();
83508366
unsigned Opc = Op.getOpcode();
8351-
assert((Opc == ISD::UINT_TO_FP || Opc == ISD::SINT_TO_FP) &&
8367+
SDValue Src = Op.getOperand(IsStrict ? 1 : 0);
8368+
assert((Opc == ISD::UINT_TO_FP || Opc == ISD::SINT_TO_FP ||
8369+
Opc == ISD::STRICT_UINT_TO_FP || Opc == ISD::STRICT_SINT_TO_FP) &&
83528370
"Unexpected conversion type");
83538371
assert((Op.getValueType() == MVT::v2f64 || Op.getValueType() == MVT::v4f32) &&
83548372
"Supports conversions to v2f64/v4f32 only.");
83558373

8356-
bool SignedConv = Opc == ISD::SINT_TO_FP;
8374+
bool SignedConv = Opc == ISD::SINT_TO_FP || Opc == ISD::STRICT_SINT_TO_FP;
83578375
bool FourEltRes = Op.getValueType() == MVT::v4f32;
83588376

8359-
SDValue Wide = widenVec(DAG, Op.getOperand(0), dl);
8377+
SDValue Wide = widenVec(DAG, Src, dl);
83608378
EVT WideVT = Wide.getValueType();
83618379
unsigned WideNumElts = WideVT.getVectorNumElements();
83628380
MVT IntermediateVT = FourEltRes ? MVT::v4i32 : MVT::v2i64;
@@ -8381,7 +8399,7 @@ SDValue PPCTargetLowering::LowerINT_TO_FPVector(SDValue Op, SelectionDAG &DAG,
83818399
SDValue Extend;
83828400
if (SignedConv) {
83838401
Arrange = DAG.getBitcast(IntermediateVT, Arrange);
8384-
EVT ExtVT = Op.getOperand(0).getValueType();
8402+
EVT ExtVT = Src.getValueType();
83858403
if (Subtarget.hasP9Altivec())
83868404
ExtVT = EVT::getVectorVT(*DAG.getContext(), WideVT.getVectorElementType(),
83878405
IntermediateVT.getVectorNumElements());
@@ -8391,6 +8409,10 @@ SDValue PPCTargetLowering::LowerINT_TO_FPVector(SDValue Op, SelectionDAG &DAG,
83918409
} else
83928410
Extend = DAG.getNode(ISD::BITCAST, dl, IntermediateVT, Arrange);
83938411

8412+
if (IsStrict)
8413+
return DAG.getNode(Opc, dl, {Op.getValueType(), MVT::Other},
8414+
{Op.getOperand(0), Extend});
8415+
83948416
return DAG.getNode(Opc, dl, Op.getValueType(), Extend);
83958417
}
83968418

@@ -10648,6 +10670,28 @@ SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
1064810670
}
1064910671
}
1065010672

10673+
void PPCTargetLowering::LowerOperationWrapper(SDNode *N,
10674+
SmallVectorImpl<SDValue> &Results,
10675+
SelectionDAG &DAG) const {
10676+
SDValue Res = LowerOperation(SDValue(N, 0), DAG);
10677+
10678+
if (!Res.getNode())
10679+
return;
10680+
10681+
// Take the return value as-is if original node has only one result.
10682+
if (N->getNumValues() == 1) {
10683+
Results.push_back(Res);
10684+
return;
10685+
}
10686+
10687+
// New node should have the same number of results.
10688+
assert((N->getNumValues() == Res->getNumValues()) &&
10689+
"Lowering returned the wrong number of results!");
10690+
10691+
for (unsigned i = 0; i < N->getNumValues(); ++i)
10692+
Results.push_back(Res.getValue(i));
10693+
}
10694+
1065110695
void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
1065210696
SmallVectorImpl<SDValue>&Results,
1065310697
SelectionDAG &DAG) const {

‎llvm/lib/Target/PowerPC/PPCISelLowering.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -753,6 +753,12 @@ namespace llvm {
753753
///
754754
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
755755

756+
/// LowerOperationWrapper - Place custom new result values for node in
757+
/// Results.
758+
void LowerOperationWrapper(SDNode *N,
759+
SmallVectorImpl<SDValue> &Results,
760+
SelectionDAG &DAG) const override;
761+
756762
/// ReplaceNodeResults - Replace the results of node with an illegal result
757763
/// type with new values built out of custom code.
758764
///

‎llvm/lib/Target/PowerPC/PPCInstrVSX.td

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -821,15 +821,15 @@ let hasSideEffects = 0 in {
821821
def XVCVDPSXDS : XX2Form<60, 472,
822822
(outs vsrc:$XT), (ins vsrc:$XB),
823823
"xvcvdpsxds $XT, $XB", IIC_VecFP,
824-
[(set v2i64:$XT, (fp_to_sint v2f64:$XB))]>;
824+
[(set v2i64:$XT, (any_fp_to_sint v2f64:$XB))]>;
825825
def XVCVDPSXWS : XX2Form<60, 216,
826826
(outs vsrc:$XT), (ins vsrc:$XB),
827827
"xvcvdpsxws $XT, $XB", IIC_VecFP,
828828
[(set v4i32:$XT, (int_ppc_vsx_xvcvdpsxws v2f64:$XB))]>;
829829
def XVCVDPUXDS : XX2Form<60, 456,
830830
(outs vsrc:$XT), (ins vsrc:$XB),
831831
"xvcvdpuxds $XT, $XB", IIC_VecFP,
832-
[(set v2i64:$XT, (fp_to_uint v2f64:$XB))]>;
832+
[(set v2i64:$XT, (any_fp_to_uint v2f64:$XB))]>;
833833
def XVCVDPUXWS : XX2Form<60, 200,
834834
(outs vsrc:$XT), (ins vsrc:$XB),
835835
"xvcvdpuxws $XT, $XB", IIC_VecFP,
@@ -845,18 +845,18 @@ let hasSideEffects = 0 in {
845845
def XVCVSPSXWS : XX2Form<60, 152,
846846
(outs vsrc:$XT), (ins vsrc:$XB),
847847
"xvcvspsxws $XT, $XB", IIC_VecFP,
848-
[(set v4i32:$XT, (fp_to_sint v4f32:$XB))]>;
848+
[(set v4i32:$XT, (any_fp_to_sint v4f32:$XB))]>;
849849
def XVCVSPUXDS : XX2Form<60, 392,
850850
(outs vsrc:$XT), (ins vsrc:$XB),
851851
"xvcvspuxds $XT, $XB", IIC_VecFP, []>;
852852
def XVCVSPUXWS : XX2Form<60, 136,
853853
(outs vsrc:$XT), (ins vsrc:$XB),
854854
"xvcvspuxws $XT, $XB", IIC_VecFP,
855-
[(set v4i32:$XT, (fp_to_uint v4f32:$XB))]>;
855+
[(set v4i32:$XT, (any_fp_to_uint v4f32:$XB))]>;
856856
def XVCVSXDDP : XX2Form<60, 504,
857857
(outs vsrc:$XT), (ins vsrc:$XB),
858858
"xvcvsxddp $XT, $XB", IIC_VecFP,
859-
[(set v2f64:$XT, (sint_to_fp v2i64:$XB))]>;
859+
[(set v2f64:$XT, (any_sint_to_fp v2i64:$XB))]>;
860860
def XVCVSXDSP : XX2Form<60, 440,
861861
(outs vsrc:$XT), (ins vsrc:$XB),
862862
"xvcvsxdsp $XT, $XB", IIC_VecFP,
@@ -868,11 +868,11 @@ let hasSideEffects = 0 in {
868868
def XVCVSXWSP : XX2Form<60, 184,
869869
(outs vsrc:$XT), (ins vsrc:$XB),
870870
"xvcvsxwsp $XT, $XB", IIC_VecFP,
871-
[(set v4f32:$XT, (sint_to_fp v4i32:$XB))]>;
871+
[(set v4f32:$XT, (any_sint_to_fp v4i32:$XB))]>;
872872
def XVCVUXDDP : XX2Form<60, 488,
873873
(outs vsrc:$XT), (ins vsrc:$XB),
874874
"xvcvuxddp $XT, $XB", IIC_VecFP,
875-
[(set v2f64:$XT, (uint_to_fp v2i64:$XB))]>;
875+
[(set v2f64:$XT, (any_uint_to_fp v2i64:$XB))]>;
876876
def XVCVUXDSP : XX2Form<60, 424,
877877
(outs vsrc:$XT), (ins vsrc:$XB),
878878
"xvcvuxdsp $XT, $XB", IIC_VecFP,
@@ -884,7 +884,7 @@ let hasSideEffects = 0 in {
884884
def XVCVUXWSP : XX2Form<60, 168,
885885
(outs vsrc:$XT), (ins vsrc:$XB),
886886
"xvcvuxwsp $XT, $XB", IIC_VecFP,
887-
[(set v4f32:$XT, (uint_to_fp v4i32:$XB))]>;
887+
[(set v4f32:$XT, (any_uint_to_fp v4i32:$XB))]>;
888888

889889
// Rounding Instructions respecting current rounding mode
890890
def XSRDPIC : XX2Form<60, 107,

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