Skip to content

Commit 2dd74d4

Browse files
momchil-velikovmomchil-velikov
authored
[AArch64] Add assembly/disassembly for FMOP4A (widening, 2-way, FP8 to FP16) instructions (llvm#113348)
The new instructions are described in https://developer.arm.com/documentation/ddi0602/2024-09/SME-Instructions
1 parent 790cbee commit 2dd74d4

File tree

4 files changed

+251
-0
lines changed

4 files changed

+251
-0
lines changed

‎llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1071,6 +1071,7 @@ let Predicates = [HasSME2p2, HasSMEF8F32], Uses = [FPMR, FPCR] in {
10711071

10721072
let Predicates = [HasSME2p2, HasSMEF8F16], Uses = [FPMR, FPCR] in {
10731073
def FTMOPA_M2ZZZI_BtoH : sme_tmopa_16b<0b01001, ZZ_b_mul_r, ZPR8, "ftmopa">;
1074+
defm FMOP4A : sme2_fmop4a_fp8_fp16_2way<"fmop4a">;
10741075
} // [HasSME2p2, HasSMEF8F16], Uses = [FPMR, FPCR]
10751076

10761077
let Predicates = [HasSME2p2, HasSMEF16F16] in {

‎llvm/lib/Target/AArch64/SMEInstrFormats.td

Lines changed: 35 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5704,3 +5704,38 @@ multiclass sme2_fmop4as_fp16_fp32_widening<bit S, string mnemonic> {
57045704
// Multiple vectors
57055705
def _M2Z2Z_HtoS : sme2_fp16_fp32_quarter_tile_outer_product<1, 1, S, mnemonic, ZZ_h_mul_r_Lo, ZZ_h_mul_r_Hi>;
57065706
}
5707+
5708+
class sme2_fp8_fp16_quarter_tile_outer_product<bit M, bit N, string mnemonic, RegisterOperand zn_ty, RegisterOperand zm_ty>
5709+
: I<(outs TileOp16:$ZAda),
5710+
(ins TileOp16:$_ZAda, zn_ty:$Zn, zm_ty:$Zm),
5711+
mnemonic, "\t$ZAda, $Zn, $Zm",
5712+
"", []>, Sched<[]> {
5713+
bit ZAda;
5714+
bits<3> Zn;
5715+
bits<3> Zm;
5716+
5717+
let Inst{31-21} = 0b10000000001;
5718+
let Inst{20} = M;
5719+
let Inst{19-17} = Zm;
5720+
let Inst{16-10} = 0b0000000;
5721+
let Inst{9} = N;
5722+
let Inst{8-6} = Zn;
5723+
let Inst{5-1} = 0b00100;
5724+
let Inst{0} = ZAda;
5725+
5726+
let Constraints = "$ZAda = $_ZAda";
5727+
}
5728+
5729+
multiclass sme2_fmop4a_fp8_fp16_2way<string mnemonic> {
5730+
// Single vectors
5731+
def _MZZ_BtoH : sme2_fp8_fp16_quarter_tile_outer_product<0b0, 0b0, mnemonic, ZPR8Mul2_Lo, ZPR8Mul2_Hi>;
5732+
5733+
// Multiple and single vectors
5734+
def _M2ZZ_BtoH : sme2_fp8_fp16_quarter_tile_outer_product<0b0, 0b1, mnemonic, ZZ_b_mul_r_Lo, ZPR8Mul2_Hi>;
5735+
5736+
// Single and multiple vectors
5737+
def _MZ2Z_BtoH : sme2_fp8_fp16_quarter_tile_outer_product<0b1, 0b0, mnemonic, ZPR8Mul2_Lo, ZZ_b_mul_r_Hi>;
5738+
5739+
// Multiple vectors
5740+
def _M2Z2Z_BtoH : sme2_fp8_fp16_quarter_tile_outer_product<0b1, 0b1, mnemonic, ZZ_b_mul_r_Lo, ZZ_b_mul_r_Hi>;
5741+
}

‎llvm/test/MC/AArch64/SME2p2/fmop4a-fp8-fp16-widening-diagnostics.s

Lines changed: 120 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,120 @@
1+
// RUN: not llvm-mc -triple=aarch64 -mattr=+sme2p2,+sme-f8f16 < %s 2>&1 | FileCheck %s
2+
3+
// Single vectors
4+
5+
fmop4a za0.d, z0.b, z16.b
6+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand
7+
8+
fmop4a za2.h, z0.b, z16.b
9+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
10+
11+
fmop4a za0.h, z0.s, z16.b
12+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.b..z14.b
13+
14+
fmop4a za0.h, z15.b, z16.b
15+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.b..z14.b
16+
17+
fmop4a za0.h, z16.b, z16.b
18+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.b..z14.b
19+
20+
fmop4a za0.h, z0.b, z16.s
21+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.b..z30.b
22+
23+
fmop4a za0.h, z12.b, z17.b
24+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.b..z30.b
25+
26+
fmop4a za0.h, z12.b, z14.b
27+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.b..z30.b
28+
29+
fmop4a za0.h, z12.b, z31.b
30+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.b..z30.b
31+
32+
// Single and multiple vectors
33+
34+
fmop4a za0.d, z0.b, {z16.b-z17.b}
35+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand
36+
37+
fmop4a za2.h, z0.b, {z16.b-z17.b}
38+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
39+
40+
fmop4a za0.h, z0.s, {z16.b-z17.b}
41+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.b..z14.b
42+
43+
fmop4a za0.h, z1.b, {z16.b-z17.b}
44+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.b..z14.b
45+
46+
fmop4a za0.h, z16.b, {z16.b-z17.b}
47+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.b..z14.b
48+
49+
fmop4a za0.h, z0.b, {z16.s-z17.s}
50+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
51+
52+
fmop4a za0.h, z0.b, {z17.b-z18.b}
53+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types
54+
55+
fmop4a za0.h, z0.b, {z16.b-z18.b}
56+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
57+
58+
fmop4a za0.h, z0.b, {z12.b-z13.b}
59+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types
60+
61+
// Multiple and single vectors
62+
63+
fmop4a za0.d, {z0.b-z1.b}, z16.b
64+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand
65+
66+
fmop4a za2.h, {z0.b-z1.b}, z16.b
67+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
68+
69+
fmop4a za0.h, {z0.s-z1.b}, z16.b
70+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
71+
72+
fmop4a za0.h, {z1.b-z2.b}, z16.b
73+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types
74+
75+
fmop4a za2.h, {z0.b-z2.b}, z16.b
76+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
77+
78+
fmop4a za0.h, {z16.b-z17.b}, z16.b
79+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types
80+
81+
fmop4a za0.h, {z0.b-z1.b}, z16.d
82+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.b..z30.b
83+
84+
fmop4a za0.h, {z0.b-z1.b}, z17.b
85+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.b..z30.b
86+
87+
fmop4a za0.h, {z0.b-z1.b}, z12.b
88+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.b..z30.b
89+
90+
// Multiple vectors
91+
92+
fmop4a za0.d, {z0.b-z1.b}, {z16.b-z17.b}
93+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand
94+
95+
fmop4a za2.h, {z0.b-z1.b}, {z16.b-z17.b}
96+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
97+
98+
fmop4a za0.h, {z0.s-z1.s}, {z16.b-z17.b}
99+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
100+
101+
fmop4a za0.h, {z1.b-z2.b}, {z16.b-z17.b}
102+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types
103+
104+
fmop4a za0.h, {z0.b-z2.b}, {z16.b-z17.b}
105+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
106+
107+
fmop4a za0.h, {z18.b-z19.b}, {z16.b-z17.b}
108+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types
109+
110+
fmop4a za0.h, {z0.b-z1.b}, {z16.s-z17.s}
111+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
112+
113+
fmop4a za0.h, {z0.b-z1.b}, {z19.b-z20.b}
114+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types
115+
116+
fmop4a za0.h, {z0.b-z1.b}, {z18.b-z20.b}
117+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
118+
119+
fmop4a za0.h, {z0.b-z1.b}, {z10.b-z11.b}
120+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types

‎llvm/test/MC/AArch64/SME2p2/fmop4a-fp8-fp16-widening.s

Lines changed: 95 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,95 @@
1+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-f8f16 < %s \
2+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3+
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
4+
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
5+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2,+sme-f8f16 < %s \
6+
// RUN: | llvm-objdump -d --mattr=+sme2p2,+sme-f8f16 - | FileCheck %s --check-prefix=CHECK-INST
7+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2,+sme-f8f16 < %s \
8+
// RUN: | llvm-objdump -d --mattr=-sme2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
9+
// Disassemble encoding and check the re-encoding (-show-encoding) matches.
10+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-f8f16 < %s \
11+
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
12+
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p2,+sme-f8f16 -disassemble -show-encoding \
13+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
14+
15+
// Single vectors
16+
17+
fmop4a za0.h, z0.b, z16.b // 10000000-00100000-00000000-00001000
18+
// CHECK-INST: fmop4a za0.h, z0.b, z16.b
19+
// CHECK-ENCODING: [0x08,0x00,0x20,0x80]
20+
// CHECK-ERROR: instruction requires: sme2p2 sme-f8f16
21+
// CHECK-UNKNOWN: 80200008 <unknown>
22+
23+
fmop4a za1.h, z12.b, z24.b // 10000000-00101000-00000001-10001001
24+
// CHECK-INST: fmop4a za1.h, z12.b, z24.b
25+
// CHECK-ENCODING: [0x89,0x01,0x28,0x80]
26+
// CHECK-ERROR: instruction requires: sme2p2 sme-f8f16
27+
// CHECK-UNKNOWN: 80280189 <unknown>
28+
29+
fmop4a za1.h, z14.b, z30.b // 10000000-00101110-00000001-11001001
30+
// CHECK-INST: fmop4a za1.h, z14.b, z30.b
31+
// CHECK-ENCODING: [0xc9,0x01,0x2e,0x80]
32+
// CHECK-ERROR: instruction requires: sme2p2 sme-f8f16
33+
// CHECK-UNKNOWN: 802e01c9 <unknown>
34+
35+
// Single and multiple vectors
36+
37+
fmop4a za0.h, z0.b, {z16.b-z17.b} // 10000000-00110000-00000000-00001000
38+
// CHECK-INST: fmop4a za0.h, z0.b, { z16.b, z17.b }
39+
// CHECK-ENCODING: [0x08,0x00,0x30,0x80]
40+
// CHECK-ERROR: instruction requires: sme2p2 sme-f8f16
41+
// CHECK-UNKNOWN: 80300008 <unknown>
42+
43+
fmop4a za1.h, z10.b, {z20.b-z21.b} // 10000000-00110100-00000001-01001001
44+
// CHECK-INST: fmop4a za1.h, z10.b, { z20.b, z21.b }
45+
// CHECK-ENCODING: [0x49,0x01,0x34,0x80]
46+
// CHECK-ERROR: instruction requires: sme2p2 sme-f8f16
47+
// CHECK-UNKNOWN: 80340149 <unknown>
48+
49+
fmop4a za1.h, z14.b, {z30.b-z31.b} // 10000000-00111110-00000001-11001001
50+
// CHECK-INST: fmop4a za1.h, z14.b, { z30.b, z31.b }
51+
// CHECK-ENCODING: [0xc9,0x01,0x3e,0x80]
52+
// CHECK-ERROR: instruction requires: sme2p2 sme-f8f16
53+
// CHECK-UNKNOWN: 803e01c9 <unknown>
54+
55+
// Multiple and single vectors
56+
57+
fmop4a za0.h, {z0.b-z1.b}, z16.b // 10000000-00100000-00000010-00001000
58+
// CHECK-INST: fmop4a za0.h, { z0.b, z1.b }, z16.b
59+
// CHECK-ENCODING: [0x08,0x02,0x20,0x80]
60+
// CHECK-ERROR: instruction requires: sme2p2 sme-f8f16
61+
// CHECK-UNKNOWN: 80200208 <unknown>
62+
63+
fmop4a za1.h, {z10.b-z11.b}, z20.b // 10000000-00100100-00000011-01001001
64+
// CHECK-INST: fmop4a za1.h, { z10.b, z11.b }, z20.b
65+
// CHECK-ENCODING: [0x49,0x03,0x24,0x80]
66+
// CHECK-ERROR: instruction requires: sme2p2 sme-f8f16
67+
// CHECK-UNKNOWN: 80240349 <unknown>
68+
69+
fmop4a za1.h, {z14.b-z15.b}, z30.b // 10000000-00101110-00000011-11001001
70+
// CHECK-INST: fmop4a za1.h, { z14.b, z15.b }, z30.b
71+
// CHECK-ENCODING: [0xc9,0x03,0x2e,0x80]
72+
// CHECK-ERROR: instruction requires: sme2p2 sme-f8f16
73+
// CHECK-UNKNOWN: 802e03c9 <unknown>
74+
75+
76+
// Multiple vectors
77+
78+
fmop4a za0.h, {z0.b-z1.b}, {z16.b-z17.b} // 10000000-00110000-00000010-00001000
79+
// CHECK-INST: fmop4a za0.h, { z0.b, z1.b }, { z16.b, z17.b }
80+
// CHECK-ENCODING: [0x08,0x02,0x30,0x80]
81+
// CHECK-ERROR: instruction requires: sme2p2 sme-f8f16
82+
// CHECK-UNKNOWN: 80300208 <unknown>
83+
84+
fmop4a za1.h, {z10.b-z11.b}, {z20.b-z21.b} // 10000000-00110100-00000011-01001001
85+
// CHECK-INST: fmop4a za1.h, { z10.b, z11.b }, { z20.b, z21.b }
86+
// CHECK-ENCODING: [0x49,0x03,0x34,0x80]
87+
// CHECK-ERROR: instruction requires: sme2p2 sme-f8f16
88+
// CHECK-UNKNOWN: 80340349 <unknown>
89+
90+
fmop4a za1.h, {z14.b-z15.b}, {z30.b-z31.b} // 10000000-00111110-00000011-11001001
91+
// CHECK-INST: fmop4a za1.h, { z14.b, z15.b }, { z30.b, z31.b }
92+
// CHECK-ENCODING: [0xc9,0x03,0x3e,0x80]
93+
// CHECK-ERROR: instruction requires: sme2p2 sme-f8f16
94+
// CHECK-UNKNOWN: 803e03c9 <unknown>
95+

0 commit comments

Comments
 (0)