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[PowerPC] Support constrained scalar fptosi/fptoui
This patch adds support for constrained scalar fp to int operations on PowerPC. Besides, this fixes the FP exception bit of quad-precision convert & truncate instructions. Reviewed By: steven.zhang, uweigand Differential Revision: https://reviews.llvm.org/D81537
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7 files changed

+911
-42
lines changed

7 files changed

+911
-42
lines changed

‎llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Lines changed: 83 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -450,6 +450,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
450450
setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
451451
} else {
452452
// PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
453+
setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
453454
setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
454455

455456
// PowerPC does not have [U|S]INT_TO_FP
@@ -582,12 +583,15 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
582583

583584
if (Subtarget.has64BitSupport()) {
584585
// They also have instructions for converting between i64 and fp.
586+
setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i64, Custom);
587+
setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i64, Expand);
585588
setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
586589
setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
587590
setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
588591
setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
589592
// This is just the low 32 bits of a (signed) fp->i64 conversion.
590593
// We cannot do this with Promote because i64 is not a legal type.
594+
setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
591595
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
592596

593597
if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
@@ -597,19 +601,25 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
597601
if (Subtarget.hasSPE()) {
598602
setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Legal);
599603
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
600-
} else
604+
} else {
605+
setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Expand);
601606
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
607+
}
602608
}
603609

604610
// With the instructions enabled under FPCVT, we can do everything.
605611
if (Subtarget.hasFPCVT()) {
606612
if (Subtarget.has64BitSupport()) {
613+
setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i64, Custom);
614+
setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i64, Custom);
607615
setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
608616
setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
609617
setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
610618
setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
611619
}
612620

621+
setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
622+
setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
613623
setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
614624
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
615625
setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
@@ -1464,6 +1474,14 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
14641474
case PPCISD::MAT_PCREL_ADDR: return "PPCISD::MAT_PCREL_ADDR";
14651475
case PPCISD::LD_SPLAT: return "PPCISD::LD_SPLAT";
14661476
case PPCISD::FNMSUB: return "PPCISD::FNMSUB";
1477+
case PPCISD::STRICT_FCTIDZ:
1478+
return "PPCISD::STRICT_FCTIDZ";
1479+
case PPCISD::STRICT_FCTIWZ:
1480+
return "PPCISD::STRICT_FCTIWZ";
1481+
case PPCISD::STRICT_FCTIDUZ:
1482+
return "PPCISD::STRICT_FCTIDUZ";
1483+
case PPCISD::STRICT_FCTIWUZ:
1484+
return "PPCISD::STRICT_FCTIWUZ";
14671485
}
14681486
return nullptr;
14691487
}
@@ -7938,28 +7956,57 @@ SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
79387956
return Op;
79397957
}
79407958

7959+
static unsigned getPPCStrictOpcode(unsigned Opc) {
7960+
switch (Opc) {
7961+
default:
7962+
llvm_unreachable("No strict version of this opcode!");
7963+
case PPCISD::FCTIDZ:
7964+
return PPCISD::STRICT_FCTIDZ;
7965+
case PPCISD::FCTIWZ:
7966+
return PPCISD::STRICT_FCTIWZ;
7967+
case PPCISD::FCTIDUZ:
7968+
return PPCISD::STRICT_FCTIDUZ;
7969+
case PPCISD::FCTIWUZ:
7970+
return PPCISD::STRICT_FCTIWUZ;
7971+
}
7972+
}
7973+
79417974
static SDValue convertFPToInt(SDValue Op, SelectionDAG &DAG,
79427975
const PPCSubtarget &Subtarget) {
79437976
SDLoc dl(Op);
7944-
bool IsSigned = Op.getOpcode() == ISD::FP_TO_SINT;
7945-
SDValue Src = Op.getOperand(0);
7977+
bool IsStrict = Op->isStrictFPOpcode();
7978+
bool IsSigned = Op.getOpcode() == ISD::FP_TO_SINT ||
7979+
Op.getOpcode() == ISD::STRICT_FP_TO_SINT;
7980+
// For strict nodes, source is the second operand.
7981+
SDValue Src = Op.getOperand(IsStrict ? 1 : 0);
7982+
SDValue Chain = IsStrict ? Op.getOperand(0) : SDValue();
79467983
assert(Src.getValueType().isFloatingPoint());
7947-
if (Src.getValueType() == MVT::f32)
7948-
Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
7984+
if (Src.getValueType() == MVT::f32) {
7985+
if (IsStrict) {
7986+
Src = DAG.getNode(ISD::STRICT_FP_EXTEND, dl, {MVT::f64, MVT::Other},
7987+
{Chain, Src});
7988+
Chain = Src.getValue(1);
7989+
} else
7990+
Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
7991+
}
79497992
SDValue Conv;
7993+
unsigned Opc = ISD::DELETED_NODE;
79507994
switch (Op.getSimpleValueType().SimpleTy) {
79517995
default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
79527996
case MVT::i32:
7953-
Conv = DAG.getNode(
7954-
IsSigned ? PPCISD::FCTIWZ
7955-
: (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ),
7956-
dl, MVT::f64, Src);
7997+
Opc = IsSigned ? PPCISD::FCTIWZ
7998+
: (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ);
79577999
break;
79588000
case MVT::i64:
79598001
assert((IsSigned || Subtarget.hasFPCVT()) &&
79608002
"i64 FP_TO_UINT is supported only with FPCVT");
7961-
Conv = DAG.getNode(IsSigned ? PPCISD::FCTIDZ : PPCISD::FCTIDUZ, dl,
7962-
MVT::f64, Src);
8003+
Opc = IsSigned ? PPCISD::FCTIDZ : PPCISD::FCTIDUZ;
8004+
}
8005+
if (IsStrict) {
8006+
Opc = getPPCStrictOpcode(Opc);
8007+
Conv = DAG.getNode(Opc, dl, {MVT::f64, MVT::Other}, {Chain, Src});
8008+
} else {
8009+
Conv = DAG.getNode(Opc, dl, MVT::f64, Src);
79638010
}
79648011
return Conv;
79658012
}
@@ -7968,7 +8015,9 @@ void PPCTargetLowering::LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
79688015
SelectionDAG &DAG,
79698016
const SDLoc &dl) const {
79708017
SDValue Tmp = convertFPToInt(Op, DAG, Subtarget);
7971-
bool IsSigned = Op.getOpcode() == ISD::FP_TO_SINT;
8018+
bool IsSigned = Op.getOpcode() == ISD::FP_TO_SINT ||
8019+
Op.getOpcode() == ISD::STRICT_FP_TO_SINT;
8020+
bool IsStrict = Op->isStrictFPOpcode();
79728021

79738022
// Convert the FP value to an int value through memory.
79748023
bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
@@ -7979,18 +8028,18 @@ void PPCTargetLowering::LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
79798028
MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
79808029

79818030
// Emit a store to the stack slot.
7982-
SDValue Chain;
8031+
SDValue Chain = IsStrict ? Tmp.getValue(1) : DAG.getEntryNode();
79838032
Align Alignment(DAG.getEVTAlign(Tmp.getValueType()));
79848033
if (i32Stack) {
79858034
MachineFunction &MF = DAG.getMachineFunction();
79868035
Alignment = Align(4);
79878036
MachineMemOperand *MMO =
79888037
MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, Alignment);
7989-
SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
8038+
SDValue Ops[] = { Chain, Tmp, FIPtr };
79908039
Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
79918040
DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
79928041
} else
7993-
Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr, MPI, Alignment);
8042+
Chain = DAG.getStore(Chain, dl, Tmp, FIPtr, MPI, Alignment);
79948043

79958044
// Result is a load from the stack slot. If loading 4 bytes, make sure to
79968045
// add in a bias on big endian.
@@ -8012,23 +8061,29 @@ void PPCTargetLowering::LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
80128061
SDValue PPCTargetLowering::LowerFP_TO_INTDirectMove(SDValue Op,
80138062
SelectionDAG &DAG,
80148063
const SDLoc &dl) const {
8015-
assert(Op.getOperand(0).getValueType().isFloatingPoint());
8016-
return DAG.getNode(PPCISD::MFVSR, dl, Op.getSimpleValueType().SimpleTy,
8017-
convertFPToInt(Op, DAG, Subtarget));
8064+
SDValue Conv = convertFPToInt(Op, DAG, Subtarget);
8065+
SDValue Mov = DAG.getNode(PPCISD::MFVSR, dl, Op.getValueType(), Conv);
8066+
if (Op->isStrictFPOpcode())
8067+
return DAG.getMergeValues({Mov, Conv.getValue(1)}, dl);
8068+
else
8069+
return Mov;
80188070
}
80198071

80208072
SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
80218073
const SDLoc &dl) const {
8022-
SDValue Src = Op.getOperand(0);
8074+
bool IsStrict = Op->isStrictFPOpcode();
8075+
bool IsSigned = Op.getOpcode() == ISD::FP_TO_SINT ||
8076+
Op.getOpcode() == ISD::STRICT_FP_TO_SINT;
8077+
SDValue Src = Op.getOperand(IsStrict ? 1 : 0);
80238078
// FP to INT conversions are legal for f128.
80248079
if (Src.getValueType() == MVT::f128)
80258080
return Op;
80268081

80278082
// Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on
80288083
// PPC (the libcall is not available).
8029-
if (Src.getValueType() == MVT::ppcf128) {
8084+
if (Src.getValueType() == MVT::ppcf128 && !IsStrict) {
80308085
if (Op.getValueType() == MVT::i32) {
8031-
if (Op.getOpcode() == ISD::FP_TO_SINT) {
8086+
if (IsSigned) {
80328087
SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::f64, Src,
80338088
DAG.getIntPtrConstant(0, dl));
80348089
SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::f64, Src,
@@ -8039,8 +8094,7 @@ SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
80398094

80408095
// Now use a smaller FP_TO_SINT.
80418096
return DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Res);
8042-
}
8043-
if (Op.getOpcode() == ISD::FP_TO_UINT) {
8097+
} else {
80448098
const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
80458099
APFloat APF = APFloat(APFloat::PPCDoubleDouble(), APInt(128, TwoE31));
80468100
SDValue Tmp = DAG.getConstantFP(APF, dl, MVT::ppcf128);
@@ -10458,6 +10512,8 @@ SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
1045810512
case ISD::STORE: return LowerSTORE(Op, DAG);
1045910513
case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
1046010514
case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
10515+
case ISD::STRICT_FP_TO_UINT:
10516+
case ISD::STRICT_FP_TO_SINT:
1046110517
case ISD::FP_TO_UINT:
1046210518
case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG, SDLoc(Op));
1046310519
case ISD::UINT_TO_FP:
@@ -10548,10 +10604,13 @@ void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
1054810604
}
1054910605
return;
1055010606
}
10607+
case ISD::STRICT_FP_TO_SINT:
10608+
case ISD::STRICT_FP_TO_UINT:
1055110609
case ISD::FP_TO_SINT:
1055210610
case ISD::FP_TO_UINT:
1055310611
// LowerFP_TO_INT() can only handle f32 and f64.
10554-
if (N->getOperand(0).getValueType() == MVT::ppcf128)
10612+
if (N->getOperand(N->isStrictFPOpcode() ? 1 : 0).getValueType() ==
10613+
MVT::ppcf128)
1055510614
return;
1055610615
Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
1055710616
return;

‎llvm/lib/Target/PowerPC/PPCISelLowering.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -436,6 +436,12 @@ namespace llvm {
436436
/// PLD.
437437
MAT_PCREL_ADDR,
438438

439+
// Constrained conversion from floating point to int
440+
STRICT_FCTIDZ = ISD::FIRST_TARGET_STRICTFP_OPCODE,
441+
STRICT_FCTIWZ,
442+
STRICT_FCTIDUZ,
443+
STRICT_FCTIWUZ,
444+
439445
/// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
440446
/// byte-swapping store instruction. It byte-swaps the low "Type" bits of
441447
/// the GPRC input, then stores it through Ptr. Type can be either i16 or

‎llvm/lib/Target/PowerPC/PPCInstr64Bit.td

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1457,7 +1457,7 @@ defm FCTIDU : XForm_26r<63, 942, (outs f8rc:$frD), (ins f8rc:$frB),
14571457
[]>, isPPC64;
14581458
defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB),
14591459
"fctidz", "$frD, $frB", IIC_FPGeneral,
1460-
[(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64;
1460+
[(set f64:$frD, (PPCany_fctidz f64:$frB))]>, isPPC64;
14611461

14621462
defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB),
14631463
"fcfidu", "$frD, $frB", IIC_FPGeneral,
@@ -1470,10 +1470,10 @@ defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB),
14701470
[(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64;
14711471
defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB),
14721472
"fctiduz", "$frD, $frB", IIC_FPGeneral,
1473-
[(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64;
1473+
[(set f64:$frD, (PPCany_fctiduz f64:$frB))]>, isPPC64;
14741474
defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB),
14751475
"fctiwuz", "$frD, $frB", IIC_FPGeneral,
1476-
[(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64;
1476+
[(set f64:$frD, (PPCany_fctiwuz f64:$frB))]>, isPPC64;
14771477
}
14781478

14791479

‎llvm/lib/Target/PowerPC/PPCInstrInfo.td

Lines changed: 23 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -215,6 +215,28 @@ def PPCfnmsub : SDNode<"PPCISD::FNMSUB" , SDTFPTernaryOp>;
215215

216216
def PPCextswsli : SDNode<"PPCISD::EXTSWSLI" , SDT_PPCextswsli>;
217217

218+
def PPCstrict_fctidz : SDNode<"PPCISD::STRICT_FCTIDZ",
219+
SDTFPUnaryOp, [SDNPHasChain]>;
220+
def PPCstrict_fctiwz : SDNode<"PPCISD::STRICT_FCTIWZ",
221+
SDTFPUnaryOp, [SDNPHasChain]>;
222+
def PPCstrict_fctiduz : SDNode<"PPCISD::STRICT_FCTIDUZ",
223+
SDTFPUnaryOp, [SDNPHasChain]>;
224+
def PPCstrict_fctiwuz : SDNode<"PPCISD::STRICT_FCTIWUZ",
225+
SDTFPUnaryOp, [SDNPHasChain]>;
226+
227+
def PPCany_fctidz : PatFrags<(ops node:$op),
228+
[(PPCstrict_fctidz node:$op),
229+
(PPCfctidz node:$op)]>;
230+
def PPCany_fctiwz : PatFrags<(ops node:$op),
231+
[(PPCstrict_fctiwz node:$op),
232+
(PPCfctiwz node:$op)]>;
233+
def PPCany_fctiduz : PatFrags<(ops node:$op),
234+
[(PPCstrict_fctiduz node:$op),
235+
(PPCfctiduz node:$op)]>;
236+
def PPCany_fctiwuz : PatFrags<(ops node:$op),
237+
[(PPCstrict_fctiwuz node:$op),
238+
(PPCfctiwuz node:$op)]>;
239+
218240
// Move 2 i64 values into a VSX register
219241
def PPCbuild_fp128: SDNode<"PPCISD::BUILD_FP128",
220242
SDTypeProfile<1, 2,
@@ -2632,7 +2654,7 @@ let Uses = [RM], mayRaiseFPException = 1, hasSideEffects = 0 in {
26322654
[]>;
26332655
defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
26342656
"fctiwz", "$frD, $frB", IIC_FPGeneral,
2635-
[(set f64:$frD, (PPCfctiwz f64:$frB))]>;
2657+
[(set f64:$frD, (PPCany_fctiwz f64:$frB))]>;
26362658

26372659
defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB),
26382660
"frsp", "$frD, $frB", IIC_FPGeneral,

‎llvm/lib/Target/PowerPC/PPCInstrVSX.td

Lines changed: 13 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -769,39 +769,39 @@ let hasSideEffects = 0 in {
769769
def XSCVDPSXDS : XX2Form<60, 344,
770770
(outs vsfrc:$XT), (ins vsfrc:$XB),
771771
"xscvdpsxds $XT, $XB", IIC_VecFP,
772-
[(set f64:$XT, (PPCfctidz f64:$XB))]>;
772+
[(set f64:$XT, (PPCany_fctidz f64:$XB))]>;
773773
let isCodeGenOnly = 1 in
774774
def XSCVDPSXDSs : XX2Form<60, 344,
775775
(outs vssrc:$XT), (ins vssrc:$XB),
776776
"xscvdpsxds $XT, $XB", IIC_VecFP,
777-
[(set f32:$XT, (PPCfctidz f32:$XB))]>;
777+
[(set f32:$XT, (PPCany_fctidz f32:$XB))]>;
778778
def XSCVDPSXWS : XX2Form<60, 88,
779779
(outs vsfrc:$XT), (ins vsfrc:$XB),
780780
"xscvdpsxws $XT, $XB", IIC_VecFP,
781-
[(set f64:$XT, (PPCfctiwz f64:$XB))]>;
781+
[(set f64:$XT, (PPCany_fctiwz f64:$XB))]>;
782782
let isCodeGenOnly = 1 in
783783
def XSCVDPSXWSs : XX2Form<60, 88,
784784
(outs vssrc:$XT), (ins vssrc:$XB),
785785
"xscvdpsxws $XT, $XB", IIC_VecFP,
786-
[(set f32:$XT, (PPCfctiwz f32:$XB))]>;
786+
[(set f32:$XT, (PPCany_fctiwz f32:$XB))]>;
787787
def XSCVDPUXDS : XX2Form<60, 328,
788788
(outs vsfrc:$XT), (ins vsfrc:$XB),
789789
"xscvdpuxds $XT, $XB", IIC_VecFP,
790-
[(set f64:$XT, (PPCfctiduz f64:$XB))]>;
790+
[(set f64:$XT, (PPCany_fctiduz f64:$XB))]>;
791791
let isCodeGenOnly = 1 in
792792
def XSCVDPUXDSs : XX2Form<60, 328,
793793
(outs vssrc:$XT), (ins vssrc:$XB),
794794
"xscvdpuxds $XT, $XB", IIC_VecFP,
795-
[(set f32:$XT, (PPCfctiduz f32:$XB))]>;
795+
[(set f32:$XT, (PPCany_fctiduz f32:$XB))]>;
796796
def XSCVDPUXWS : XX2Form<60, 72,
797797
(outs vsfrc:$XT), (ins vsfrc:$XB),
798798
"xscvdpuxws $XT, $XB", IIC_VecFP,
799-
[(set f64:$XT, (PPCfctiwuz f64:$XB))]>;
799+
[(set f64:$XT, (PPCany_fctiwuz f64:$XB))]>;
800800
let isCodeGenOnly = 1 in
801801
def XSCVDPUXWSs : XX2Form<60, 72,
802802
(outs vssrc:$XT), (ins vssrc:$XB),
803803
"xscvdpuxws $XT, $XB", IIC_VecFP,
804-
[(set f32:$XT, (PPCfctiwuz f32:$XB))]>;
804+
[(set f32:$XT, (PPCany_fctiwuz f32:$XB))]>;
805805
def XSCVSPDP : XX2Form<60, 329,
806806
(outs vsfrc:$XT), (ins vsfrc:$XB),
807807
"xscvspdp $XT, $XB", IIC_VecFP, []>;
@@ -1479,9 +1479,8 @@ let Predicates = [HasVSX, HasP9Vector] in {
14791479
f128:$vB))]>;
14801480
}
14811481

1482-
// FIXME: Setting the hasSideEffects flag here to match current behaviour.
14831482
// Truncate & Convert QP -> (Un)Signed (D)Word (dword[1] is set to zero)
1484-
let hasSideEffects = 1 in {
1483+
let mayRaiseFPException = 1 in {
14851484
def XSCVQPSDZ : X_VT5_XO5_VB5<63, 25, 836, "xscvqpsdz", []>;
14861485
def XSCVQPSWZ : X_VT5_XO5_VB5<63, 9, 836, "xscvqpswz", []>;
14871486
def XSCVQPUDZ : X_VT5_XO5_VB5<63, 17, 836, "xscvqpudz", []>;
@@ -3764,11 +3763,11 @@ def : Pat<(f128 (uint_to_fp ScalarLoads.ZELi8)),
37643763
(f128 (XSCVUDQP (LXSIBZX xoaddr:$src)))>;
37653764

37663765
// Truncate & Convert QP -> (Un)Signed (D)Word.
3767-
def : Pat<(i64 (fp_to_sint f128:$src)), (i64 (MFVRD (XSCVQPSDZ $src)))>;
3768-
def : Pat<(i64 (fp_to_uint f128:$src)), (i64 (MFVRD (XSCVQPUDZ $src)))>;
3769-
def : Pat<(i32 (fp_to_sint f128:$src)),
3766+
def : Pat<(i64 (any_fp_to_sint f128:$src)), (i64 (MFVRD (XSCVQPSDZ $src)))>;
3767+
def : Pat<(i64 (any_fp_to_uint f128:$src)), (i64 (MFVRD (XSCVQPUDZ $src)))>;
3768+
def : Pat<(i32 (any_fp_to_sint f128:$src)),
37703769
(i32 (MFVSRWZ (COPY_TO_REGCLASS (XSCVQPSWZ $src), VFRC)))>;
3771-
def : Pat<(i32 (fp_to_uint f128:$src)),
3770+
def : Pat<(i32 (any_fp_to_uint f128:$src)),
37723771
(i32 (MFVSRWZ (COPY_TO_REGCLASS (XSCVQPUWZ $src), VFRC)))>;
37733772

37743773
// Instructions for store(fptosi).

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