From 642c20369845d4f35d7315cd037180c5f2415a4b Mon Sep 17 00:00:00 2001
From: Graeme Winter <graeme.winter@gmail.com>
Date: Fri, 6 Jan 2023 14:01:06 +0000
Subject: [PATCH 1/3] =?UTF-8?q?Convert=20hello=5Finterp.c:times=5Ftable=20?=
 =?UTF-8?q?to=20=C2=B5Python?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Not useful for efficient calculation of times-tables (it is not) but a nice
way to show accessing hardware registers in the rp2040 from µPython
---
 interp/interp.py | 12 ++++++++++++
 1 file changed, 12 insertions(+)
 create mode 100644 interp/interp.py

diff --git a/interp/interp.py b/interp/interp.py
new file mode 100644
index 0000000..26e2004
--- /dev/null
+++ b/interp/interp.py
@@ -0,0 +1,12 @@
+from machine import mem32
+
+# initialise lane 0 on interp: set that we are using all 32 bits
+mem32[0xD0000000 | 0xAC] = 0x1F << 10
+
+# set up 9 x table example - write to accum[0] and base[0] registers
+mem32[0xD0000000 | 0x80] = 0
+mem32[0xD0000000 | 0x88] = 9
+
+# read pop register 10 times
+for j in range(10):
+    print(mem32[0xD0000000 | 0x94])
\ No newline at end of file

From 4a6ac015d22473ea930168fc7f4e3754de638925 Mon Sep 17 00:00:00 2001
From: Graeme Winter <graeme.winter@gmail.com>
Date: Fri, 6 Jan 2023 17:55:02 +0000
Subject: [PATCH 2/3] Alias registers with sensible names

---
 interp/interp.py | 22 ++++++++++++++++++----
 1 file changed, 18 insertions(+), 4 deletions(-)

diff --git a/interp/interp.py b/interp/interp.py
index 26e2004..6de5877 100644
--- a/interp/interp.py
+++ b/interp/interp.py
@@ -1,12 +1,26 @@
+# demonstrate driving low level rp2040 functions from Python by
+# direct register access - see datasheet at 
+# https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf
+# for details
+
 from machine import mem32
 
+# base address of SIO
+SIO_BASE = 0xD0000000
+
+# INTERP0 registers
+INTERP0_ACCUM0 = 0xD0000000 + 0x80
+INTERP0_BASE0 = 0xD0000000 + 0x88
+INTERP0_POP_LANE0 = 0xD0000000 + 0x94
+INTERP0_CTRL_LANE0 = 0xD0000000 + 0xAC
+
 # initialise lane 0 on interp: set that we are using all 32 bits
-mem32[0xD0000000 | 0xAC] = 0x1F << 10
+mem32[INTERP0_CTRL_LANE0] = 0x1F << 10
 
 # set up 9 x table example - write to accum[0] and base[0] registers
-mem32[0xD0000000 | 0x80] = 0
-mem32[0xD0000000 | 0x88] = 9
+mem32[INTERP0_ACCUM0] = 0
+mem32[INTERP0_BASE0] = 9
 
 # read pop register 10 times
 for j in range(10):
-    print(mem32[0xD0000000 | 0x94])
\ No newline at end of file
+    print(mem32[INTERP0_POP_LANE0])
\ No newline at end of file

From 532a6b00e08a85dd6a5fab4cfb7d83cf79b9257e Mon Sep 17 00:00:00 2001
From: Graeme Winter <graeme.winter@gmail.com>
Date: Fri, 6 Jan 2023 18:31:42 +0000
Subject: [PATCH 3/3] Typo

---
 interp/interp.py | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/interp/interp.py b/interp/interp.py
index 6de5877..182af0d 100644
--- a/interp/interp.py
+++ b/interp/interp.py
@@ -9,10 +9,10 @@
 SIO_BASE = 0xD0000000
 
 # INTERP0 registers
-INTERP0_ACCUM0 = 0xD0000000 + 0x80
-INTERP0_BASE0 = 0xD0000000 + 0x88
-INTERP0_POP_LANE0 = 0xD0000000 + 0x94
-INTERP0_CTRL_LANE0 = 0xD0000000 + 0xAC
+INTERP0_ACCUM0 = SIO_BASE + 0x80
+INTERP0_BASE0 = SIO_BASE + 0x88
+INTERP0_POP_LANE0 = SIO_BASE + 0x94
+INTERP0_CTRL_LANE0 = SIO_BASE + 0xAC
 
 # initialise lane 0 on interp: set that we are using all 32 bits
 mem32[INTERP0_CTRL_LANE0] = 0x1F << 10