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dstogovdstogov
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Update IR
IR commit: 1689cad28a7af72043a0bc10a04ec8d9dc04b368
1 parent b9a2533 commit 5057390

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7 files changed

+527
-100
lines changed

7 files changed

+527
-100
lines changed

‎ext/opcache/jit/ir/ir.c

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2692,6 +2692,16 @@ void _ir_STORE(ir_ctx *ctx, ir_ref addr, ir_ref val)
26922692
ir_type type2;
26932693
bool guarded = 0;
26942694

2695+
if (!IR_IS_CONST_REF(val)) {
2696+
insn = &ctx->ir_base[val];
2697+
if (insn->op == IR_BITCAST
2698+
&& !IR_IS_CONST_REF(insn->op1)
2699+
&& ir_type_size[insn->type] == ir_type_size[ctx->ir_base[insn->op1].type]) {
2700+
/* skip BITCAST */
2701+
val = insn->op1;
2702+
}
2703+
}
2704+
26952705
IR_ASSERT(ctx->control);
26962706
while (ref > limit) {
26972707
insn = &ctx->ir_base[ref];

‎ext/opcache/jit/ir/ir_aarch64.dasc

Lines changed: 48 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -633,6 +633,11 @@ int ir_get_target_constraints(ir_ctx *ctx, ir_ref ref, ir_target_constraints *co
633633
constraints->tmp_regs[0] = IR_TMP_REG(3, IR_ADDR, IR_LOAD_SUB_REF, IR_SAVE_SUB_REF);
634634
n = 1;
635635
break;
636+
case IR_VA_COPY:
637+
flags = IR_OP1_MUST_BE_IN_REG | IR_OP2_MUST_BE_IN_REG;
638+
constraints->tmp_regs[0] = IR_TMP_REG(1, IR_ADDR, IR_LOAD_SUB_REF, IR_DEF_SUB_REF);
639+
n = 1;
640+
break;
636641
}
637642
constraints->tmps_count = n;
638643

@@ -4166,7 +4171,49 @@ static void ir_emit_va_start(ir_ctx *ctx, ir_ref def, ir_insn *insn)
41664171

41674172
static void ir_emit_va_copy(ir_ctx *ctx, ir_ref def, ir_insn *insn)
41684173
{
4169-
IR_ASSERT(0 && "NIY va_copy");
4174+
#ifdef __APPLE__
4175+
ir_backend_data *data = ctx->data;
4176+
dasm_State **Dst = &data->dasm_state;
4177+
ir_reg tmp_reg = ctx->regs[def][1];
4178+
ir_reg op2_reg = ctx->regs[def][2];
4179+
ir_reg op3_reg = ctx->regs[def][3];
4180+
4181+
IR_ASSERT(tmp_reg != IR_REG_NONE && op2_reg != IR_REG_NONE && op3_reg != IR_REG_NONE);
4182+
if (IR_REG_SPILLED(op2_reg)) {
4183+
op2_reg = IR_REG_NUM(op2_reg);
4184+
ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
4185+
}
4186+
if (IR_REG_SPILLED(op3_reg)) {
4187+
op3_reg = IR_REG_NUM(op3_reg);
4188+
ir_emit_load(ctx, IR_ADDR, op3_reg, insn->op3);
4189+
}
4190+
| ldr Rx(tmp_reg), [Rx(op3_reg)]
4191+
| str Rx(tmp_reg), [Rx(op2_reg)]
4192+
#else
4193+
ir_backend_data *data = ctx->data;
4194+
dasm_State **Dst = &data->dasm_state;
4195+
ir_reg tmp_reg = ctx->regs[def][1];
4196+
ir_reg op2_reg = ctx->regs[def][2];
4197+
ir_reg op3_reg = ctx->regs[def][3];
4198+
4199+
IR_ASSERT(tmp_reg != IR_REG_NONE && op2_reg != IR_REG_NONE && op3_reg != IR_REG_NONE);
4200+
if (IR_REG_SPILLED(op2_reg)) {
4201+
op2_reg = IR_REG_NUM(op2_reg);
4202+
ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
4203+
}
4204+
if (IR_REG_SPILLED(op3_reg)) {
4205+
op3_reg = IR_REG_NUM(op3_reg);
4206+
ir_emit_load(ctx, IR_ADDR, op3_reg, insn->op3);
4207+
}
4208+
| ldr Rx(tmp_reg), [Rx(op3_reg)]
4209+
| str Rx(tmp_reg), [Rx(op2_reg)]
4210+
| ldr Rx(tmp_reg), [Rx(op3_reg), #8]
4211+
| str Rx(tmp_reg), [Rx(op2_reg), #8]
4212+
| ldr Rx(tmp_reg), [Rx(op3_reg), #16]
4213+
| str Rx(tmp_reg), [Rx(op2_reg), #16]
4214+
| ldr Rx(tmp_reg), [Rx(op3_reg), #24]
4215+
| str Rx(tmp_reg), [Rx(op2_reg), #24]
4216+
#endif
41704217
}
41714218

41724219
static void ir_emit_va_arg(ir_ctx *ctx, ir_ref def, ir_insn *insn)

‎ext/opcache/jit/ir/ir_cfg.c

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1835,6 +1835,7 @@ static int ir_edge_info_cmp(const void *b1, const void *b2)
18351835

18361836
static IR_NEVER_INLINE uint32_t ir_chain_head_path_compress(ir_chain *chains, uint32_t src, uint32_t head)
18371837
{
1838+
IR_ASSERT(head != 0);
18381839
do {
18391840
head = chains[head].head;
18401841
} while (chains[head].head != head);
@@ -1997,6 +1998,9 @@ static int ir_schedule_blocks_bottom_up(ir_ctx *ctx)
19971998

19981999
/* 1. Create initial chains for each BB */
19992000
chains = ir_mem_malloc(sizeof(ir_chain) * (ctx->cfg_blocks_count + 1));
2001+
chains[0].head = 0;
2002+
chains[0].next = 0;
2003+
chains[0].prev = 0;
20002004
for (b = 1; b <= ctx->cfg_blocks_count; b++) {
20012005
chains[b].head = b;
20022006
chains[b].next = b;

‎ext/opcache/jit/ir/ir_disasm.c

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -546,6 +546,30 @@ int ir_disasm(const char *name,
546546
continue;
547547
}
548548
}
549+
} else if ((sym = ir_disasm_resolver(addr, &offset))) {
550+
r = q = strstr(p, "(%rip)");
551+
if (r && r > p) {
552+
r--;
553+
while (r > p && ((*r >= '0' && *r <= '9') || (*r >= 'a' && *r <= 'f') || (*r >= 'A' && *r <= 'F'))) {
554+
r--;
555+
}
556+
if (r > p && *r == 'x' && *(r - 1) == '0') {
557+
r -= 2;
558+
}
559+
if (r > p) {
560+
fwrite(p, 1, r - p, f);
561+
}
562+
fputs(sym, f);
563+
if (offset != 0) {
564+
if (offset > 0) {
565+
fprintf(f, "+0x%" PRIx64, offset);
566+
} else {
567+
fprintf(f, "-0x%" PRIx64, -offset);
568+
}
569+
}
570+
fprintf(f, "%s\n", q);
571+
continue;
572+
}
549573
}
550574
}
551575
#endif

‎ext/opcache/jit/ir/ir_private.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -494,6 +494,10 @@ IR_ALWAYS_INLINE void ir_sparse_set_init(ir_sparse_set *set, uint32_t size)
494494
set->size = size;
495495
set->len = 0;
496496
set->data = (uint32_t*)ir_mem_malloc(sizeof(uint32_t) * 2 * size) + size;
497+
#if IR_DEBUG
498+
/* initialize sparse part to avoid valgrind warnings */
499+
memset(&IR_SPARSE_SET_SPARSE(set, size - 1), 0, size * sizeof(uint32_t));
500+
#endif
497501
}
498502

499503
IR_ALWAYS_INLINE void ir_sparse_set_clear(ir_sparse_set *set)

‎ext/opcache/jit/ir/ir_sccp.c

Lines changed: 39 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -746,21 +746,34 @@ static bool ir_may_promote_f2d(ir_ctx *ctx, ir_ref ref)
746746
static ir_ref ir_promote_d2f(ir_ctx *ctx, ir_ref ref, ir_ref use)
747747
{
748748
ir_insn *insn = &ctx->ir_base[ref];
749+
uint32_t count;
749750

750751
IR_ASSERT(insn->type == IR_DOUBLE);
751752
if (IR_IS_CONST_REF(ref)) {
752753
return ir_const_float(ctx, (float)insn->val.d);
753754
} else {
754755
switch (insn->op) {
755756
case IR_FP2FP:
757+
count = ctx->use_lists[ref].count;
756758
ir_use_list_remove_all(ctx, ref, use);
757759
if (ctx->use_lists[ref].count == 0) {
758760
ir_use_list_replace_one(ctx, insn->op1, ref, use);
761+
if (count > 1) {
762+
do {
763+
ir_use_list_add(ctx, insn->op1, use);
764+
} while (--count > 1);
765+
}
759766
ref = insn->op1;
760767
MAKE_NOP(insn);
761768
return ref;
762769
} else {
763770
ir_use_list_add(ctx, insn->op1, use);
771+
count -= ctx->use_lists[ref].count;
772+
if (count > 1) {
773+
do {
774+
ir_use_list_add(ctx, insn->op1, use);
775+
} while (--count > 1);
776+
}
764777
}
765778
return insn->op1;
766779
// case IR_INT2FP:
@@ -796,21 +809,34 @@ static ir_ref ir_promote_d2f(ir_ctx *ctx, ir_ref ref, ir_ref use)
796809
static ir_ref ir_promote_f2d(ir_ctx *ctx, ir_ref ref, ir_ref use)
797810
{
798811
ir_insn *insn = &ctx->ir_base[ref];
812+
uint32_t count;
799813

800814
IR_ASSERT(insn->type == IR_FLOAT);
801815
if (IR_IS_CONST_REF(ref)) {
802816
return ir_const_double(ctx, (double)insn->val.f);
803817
} else {
804818
switch (insn->op) {
805819
case IR_FP2FP:
820+
count = ctx->use_lists[ref].count;
806821
ir_use_list_remove_all(ctx, ref, use);
807822
if (ctx->use_lists[ref].count == 0) {
808823
ir_use_list_replace_one(ctx, insn->op1, ref, use);
824+
if (count > 1) {
825+
do {
826+
ir_use_list_add(ctx, insn->op1, use);
827+
} while (--count > 1);
828+
}
809829
ref = insn->op1;
810830
MAKE_NOP(insn);
811831
return ref;
812832
} else {
813833
ir_use_list_add(ctx, insn->op1, use);
834+
count -= ctx->use_lists[ref].count;
835+
if (count > 1) {
836+
do {
837+
ir_use_list_add(ctx, insn->op1, use);
838+
} while (--count > 1);
839+
}
814840
}
815841
return insn->op1;
816842
case IR_INT2FP:
@@ -881,21 +907,34 @@ static bool ir_may_promote_i2i(ir_ctx *ctx, ir_type type, ir_ref ref)
881907
static ir_ref ir_promote_i2i(ir_ctx *ctx, ir_type type, ir_ref ref, ir_ref use)
882908
{
883909
ir_insn *insn = &ctx->ir_base[ref];
910+
uint32_t count;
884911

885912
if (IR_IS_CONST_REF(ref)) {
886913
return ir_const(ctx, insn->val, type);
887914
} else {
888915
switch (insn->op) {
889916
case IR_ZEXT:
890917
case IR_SEXT:
918+
count = ctx->use_lists[ref].count;
891919
ir_use_list_remove_all(ctx, ref, use);
892920
if (ctx->use_lists[ref].count == 0) {
893921
ir_use_list_replace_one(ctx, insn->op1, ref, use);
922+
if (count > 1) {
923+
do {
924+
ir_use_list_add(ctx, insn->op1, use);
925+
} while (--count > 1);
926+
}
894927
ref = insn->op1;
895928
MAKE_NOP(insn);
896929
return ref;
897930
} else {
898931
ir_use_list_add(ctx, insn->op1, use);
932+
count -= ctx->use_lists[ref].count;
933+
if (count > 1) {
934+
do {
935+
ir_use_list_add(ctx, insn->op1, use);
936+
} while (--count > 1);
937+
}
899938
}
900939
return insn->op1;
901940
case IR_NEG:

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