@@ -176,38 +176,38 @@ static void* dasm_labels[zend_lb_MAX];
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| .if X64WIN
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| gs
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| mov reg, aword [0x58]
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- | mov reg, aword [reg + tsrm_tls_index]
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- | mov reg, aword [reg + tsrm_tls_offset]
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+ | mov reg, aword [reg+ tsrm_tls_index]
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+ | mov reg, aword [reg+ tsrm_tls_offset]
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| .elif WIN
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| fs
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| mov reg, aword [0x2c]
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- | mov reg, aword [reg + tsrm_tls_index]
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- | mov reg, aword [reg + tsrm_tls_offset]
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+ | mov reg, aword [reg+ tsrm_tls_index]
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+ | mov reg, aword [reg+ tsrm_tls_offset]
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| .elif X64APPLE
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| gs
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|| if (tsrm_ls_cache_tcb_offset) {
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| mov reg, aword [tsrm_ls_cache_tcb_offset]
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|| } else {
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| mov reg, aword [tsrm_tls_index]
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- | mov reg, aword [reg + tsrm_tls_offset]
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+ | mov reg, aword [reg+ tsrm_tls_offset]
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|| }
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| .elif X64
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| fs
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|| if (tsrm_ls_cache_tcb_offset) {
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| mov reg, aword [tsrm_ls_cache_tcb_offset]
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|| } else {
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| mov reg, [0x8]
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- | mov reg, aword [reg + tsrm_tls_index]
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- | mov reg, aword [reg + tsrm_tls_offset]
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+ | mov reg, aword [reg+ tsrm_tls_index]
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+ | mov reg, aword [reg+ tsrm_tls_offset]
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|| }
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| .else
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| gs
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|| if (tsrm_ls_cache_tcb_offset) {
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| mov reg, aword [tsrm_ls_cache_tcb_offset]
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|| } else {
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| mov reg, [0x4]
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- | mov reg, aword [reg + tsrm_tls_index]
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- | mov reg, aword [reg + tsrm_tls_offset]
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+ | mov reg, aword [reg+ tsrm_tls_index]
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+ | mov reg, aword [reg+ tsrm_tls_offset]
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|| }
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| .endif
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|.endmacro
@@ -377,7 +377,7 @@ static void* dasm_labels[zend_lb_MAX];
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|.macro MEM_OP2_1_ZTS, mem_ins, prefix, struct, field, op2, tmp_reg
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| .if ZTS
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| LOAD_TSRM_CACHE tmp_reg
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- | mem_ins prefix [tmp_reg + (struct.._offset + offsetof(zend_..struct, field))], op2
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+ | mem_ins prefix [tmp_reg+ (struct.._offset+ offsetof(zend_..struct, field))], op2
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| .else
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| MEM_OP2_1 mem_ins, prefix, &struct.field, op2, tmp_reg
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| .endif
@@ -386,7 +386,7 @@ static void* dasm_labels[zend_lb_MAX];
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|.macro MEM_OP2_2_ZTS, mem_ins, op1, prefix, struct, field, tmp_reg
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| .if ZTS
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| LOAD_TSRM_CACHE tmp_reg
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- | mem_ins op1, prefix [tmp_reg + (struct.._offset + offsetof(zend_..struct, field))]
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+ | mem_ins op1, prefix [tmp_reg+ (struct.._offset+ offsetof(zend_..struct, field))]
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| .else
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| MEM_OP2_2 mem_ins, op1, prefix, &struct.field, tmp_reg
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| .endif
@@ -2867,12 +2867,47 @@ static int zend_jit_check_exception_undef_result(dasm_State **Dst, const zend_op
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return zend_jit_check_exception(Dst);
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}
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- static int zend_jit_trace_begin(dasm_State **Dst, uint32_t trace_num)
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+ static int zend_jit_trace_begin(dasm_State **Dst, uint32_t trace_num, zend_jit_trace_info *parent, uint32_t exit_num )
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{
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+ zend_regset regset = ZEND_REGSET_SCRATCH;
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+
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+ #if ZTS
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+ if (1) {
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+ #else
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+ if ((sizeof(void*) == 8 && !IS_32BIT(&EG(jit_trace_num)))) {
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+ #endif
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+ /* assignment to EG(jit_trace_num) shouldn't clober CPU register used by deoptimizer */
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+ if (parent) {
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+ int i;
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+ int parent_vars_count = parent->exit_info[exit_num].stack_size;
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+ zend_jit_trace_stack *parent_stack =
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+ parent->stack_map +
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+ parent->exit_info[exit_num].stack_offset;
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+
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+ for (i = 0; i < parent_vars_count; i++) {
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+ if (STACK_REG(parent_stack, i) != ZREG_NONE) {
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+ if (STACK_REG(parent_stack, i) < ZREG_NUM) {
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+ ZEND_REGSET_EXCL(regset, STACK_REG(parent_stack, i));
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+ } else if (STACK_REG(parent_stack, i) == ZREG_ZVAL_COPY_R0) {
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+ ZEND_REGSET_EXCL(regset, ZREG_R0);
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+ }
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+ }
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+ }
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+ }
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+ }
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+
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current_trace_num = trace_num;
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| // EG(jit_trace_num) = trace_num;
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- | MEM_OP2_1_ZTS mov, dword, executor_globals, jit_trace_num, trace_num, r0
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+ if (regset == ZEND_REGSET_EMPTY) {
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+ | push r0
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+ | MEM_OP2_1_ZTS mov, dword, executor_globals, jit_trace_num, trace_num, r0
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+ | pop r0
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+ } else {
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+ zend_reg tmp = ZEND_REGSET_FIRST(regset);
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+
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+ | MEM_OP2_1_ZTS mov, dword, executor_globals, jit_trace_num, trace_num, Ra(tmp)
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+ }
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return 1;
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}
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