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Marc Zyngierwilldeacon
Marc Zyngier
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willdeacon
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arm64: Filter out SVE hwcaps when FEAT_SVE isn't implemented
The hwcaps code that exposes SVE features to userspace only considers ID_AA64ZFR0_EL1, while this is only valid when ID_AA64PFR0_EL1.SVE advertises that SVE is actually supported. The expectations are that when ID_AA64PFR0_EL1.SVE is 0, the ID_AA64ZFR0_EL1 register is also 0. So far, so good. Things become a bit more interesting if the HW implements SME. In this case, a few ID_AA64ZFR0_EL1 fields indicate *SME* features. And these fields overlap with their SVE interpretations. But the architecture says that the SME and SVE feature sets must match, so we're still hunky-dory. This goes wrong if the HW implements SME, but not SVE. In this case, we end-up advertising some SVE features to userspace, even if the HW has none. That's because we never consider whether SVE is actually implemented. Oh well. Fix it by restricting all SVE capabilities to ID_AA64PFR0_EL1.SVE being non-zero. The HWCAPS documentation is amended to reflect the actually checks performed by the kernel. Fixes: 06a916f ("arm64: Expose SVE2 features for userspace") Reported-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org> Cc: Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: stable@vger.kernel.org Reviewed-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20250107-arm64-2024-dpisa-v5-1-7578da51fc3d@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
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‎Documentation/arch/arm64/elf_hwcaps.rst

Lines changed: 26 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -178,22 +178,28 @@ HWCAP2_DCPODP
178178
Functionality implied by ID_AA64ISAR1_EL1.DPB == 0b0010.
179179

180180
HWCAP2_SVE2
181-
Functionality implied by ID_AA64ZFR0_EL1.SVEver == 0b0001.
181+
Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
182+
ID_AA64ZFR0_EL1.SVEver == 0b0001.
182183

183184
HWCAP2_SVEAES
184-
Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0001.
185+
Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
186+
ID_AA64ZFR0_EL1.AES == 0b0001.
185187

186188
HWCAP2_SVEPMULL
187-
Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0010.
189+
Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
190+
ID_AA64ZFR0_EL1.AES == 0b0010.
188191

189192
HWCAP2_SVEBITPERM
190-
Functionality implied by ID_AA64ZFR0_EL1.BitPerm == 0b0001.
193+
Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
194+
ID_AA64ZFR0_EL1.BitPerm == 0b0001.
191195

192196
HWCAP2_SVESHA3
193-
Functionality implied by ID_AA64ZFR0_EL1.SHA3 == 0b0001.
197+
Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
198+
ID_AA64ZFR0_EL1.SHA3 == 0b0001.
194199

195200
HWCAP2_SVESM4
196-
Functionality implied by ID_AA64ZFR0_EL1.SM4 == 0b0001.
201+
Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
202+
ID_AA64ZFR0_EL1.SM4 == 0b0001.
197203

198204
HWCAP2_FLAGM2
199205
Functionality implied by ID_AA64ISAR0_EL1.TS == 0b0010.
@@ -202,16 +208,20 @@ HWCAP2_FRINT
202208
Functionality implied by ID_AA64ISAR1_EL1.FRINTTS == 0b0001.
203209

204210
HWCAP2_SVEI8MM
205-
Functionality implied by ID_AA64ZFR0_EL1.I8MM == 0b0001.
211+
Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
212+
ID_AA64ZFR0_EL1.I8MM == 0b0001.
206213

207214
HWCAP2_SVEF32MM
208-
Functionality implied by ID_AA64ZFR0_EL1.F32MM == 0b0001.
215+
Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
216+
ID_AA64ZFR0_EL1.F32MM == 0b0001.
209217

210218
HWCAP2_SVEF64MM
211-
Functionality implied by ID_AA64ZFR0_EL1.F64MM == 0b0001.
219+
Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
220+
ID_AA64ZFR0_EL1.F64MM == 0b0001.
212221

213222
HWCAP2_SVEBF16
214-
Functionality implied by ID_AA64ZFR0_EL1.BF16 == 0b0001.
223+
Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
224+
ID_AA64ZFR0_EL1.BF16 == 0b0001.
215225

216226
HWCAP2_I8MM
217227
Functionality implied by ID_AA64ISAR1_EL1.I8MM == 0b0001.
@@ -277,7 +287,8 @@ HWCAP2_EBF16
277287
Functionality implied by ID_AA64ISAR1_EL1.BF16 == 0b0010.
278288

279289
HWCAP2_SVE_EBF16
280-
Functionality implied by ID_AA64ZFR0_EL1.BF16 == 0b0010.
290+
Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
291+
ID_AA64ZFR0_EL1.BF16 == 0b0010.
281292

282293
HWCAP2_CSSC
283294
Functionality implied by ID_AA64ISAR2_EL1.CSSC == 0b0001.
@@ -286,7 +297,8 @@ HWCAP2_RPRFM
286297
Functionality implied by ID_AA64ISAR2_EL1.RPRFM == 0b0001.
287298

288299
HWCAP2_SVE2P1
289-
Functionality implied by ID_AA64ZFR0_EL1.SVEver == 0b0010.
300+
Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
301+
ID_AA64ZFR0_EL1.SVEver == 0b0010.
290302

291303
HWCAP2_SME2
292304
Functionality implied by ID_AA64SMFR0_EL1.SMEver == 0b0001.
@@ -313,7 +325,8 @@ HWCAP2_HBC
313325
Functionality implied by ID_AA64ISAR2_EL1.BC == 0b0001.
314326

315327
HWCAP2_SVE_B16B16
316-
Functionality implied by ID_AA64ZFR0_EL1.B16B16 == 0b0001.
328+
Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
329+
ID_AA64ZFR0_EL1.B16B16 == 0b0001.
317330

318331
HWCAP2_LRCPC3
319332
Functionality implied by ID_AA64ISAR1_EL1.LRCPC == 0b0011.

‎arch/arm64/kernel/cpufeature.c

Lines changed: 27 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -3008,6 +3008,13 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
30083008
.matches = match, \
30093009
}
30103010

3011+
#define HWCAP_CAP_MATCH_ID(match, reg, field, min_value, cap_type, cap) \
3012+
{ \
3013+
__HWCAP_CAP(#cap, cap_type, cap) \
3014+
HWCAP_CPUID_MATCH(reg, field, min_value) \
3015+
.matches = match, \
3016+
}
3017+
30113018
#ifdef CONFIG_ARM64_PTR_AUTH
30123019
static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
30133020
{
@@ -3036,6 +3043,13 @@ static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
30363043
};
30373044
#endif
30383045

3046+
#ifdef CONFIG_ARM64_SVE
3047+
static bool has_sve_feature(const struct arm64_cpu_capabilities *cap, int scope)
3048+
{
3049+
return system_supports_sve() && has_user_cpuid_feature(cap, scope);
3050+
}
3051+
#endif
3052+
30393053
static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
30403054
HWCAP_CAP(ID_AA64ISAR0_EL1, AES, PMULL, CAP_HWCAP, KERNEL_HWCAP_PMULL),
30413055
HWCAP_CAP(ID_AA64ISAR0_EL1, AES, AES, CAP_HWCAP, KERNEL_HWCAP_AES),
@@ -3078,19 +3092,19 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
30783092
HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT),
30793093
#ifdef CONFIG_ARM64_SVE
30803094
HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE),
3081-
HWCAP_CAP(ID_AA64ZFR0_EL1, SVEver, SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1),
3082-
HWCAP_CAP(ID_AA64ZFR0_EL1, SVEver, SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
3083-
HWCAP_CAP(ID_AA64ZFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
3084-
HWCAP_CAP(ID_AA64ZFR0_EL1, AES, PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
3085-
HWCAP_CAP(ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
3086-
HWCAP_CAP(ID_AA64ZFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_B16B16),
3087-
HWCAP_CAP(ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16),
3088-
HWCAP_CAP(ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16),
3089-
HWCAP_CAP(ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
3090-
HWCAP_CAP(ID_AA64ZFR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
3091-
HWCAP_CAP(ID_AA64ZFR0_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM),
3092-
HWCAP_CAP(ID_AA64ZFR0_EL1, F32MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM),
3093-
HWCAP_CAP(ID_AA64ZFR0_EL1, F64MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM),
3095+
HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1),
3096+
HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
3097+
HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
3098+
HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
3099+
HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
3100+
HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_B16B16),
3101+
HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16),
3102+
HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16),
3103+
HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
3104+
HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
3105+
HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM),
3106+
HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F32MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM),
3107+
HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F64MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM),
30943108
#endif
30953109
#ifdef CONFIG_ARM64_GCS
30963110
HWCAP_CAP(ID_AA64PFR1_EL1, GCS, IMP, CAP_HWCAP, KERNEL_HWCAP_GCS),

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