From ffccbc6c240295fb0b02e6717e188a64e67fdd86 Mon Sep 17 00:00:00 2001 From: Fernando Date: Wed, 28 Feb 2018 18:16:37 +0000 Subject: [PATCH 1/5] Add interpolation order parameter --- nipype/interfaces/niftyreg/regutils.py | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/nipype/interfaces/niftyreg/regutils.py b/nipype/interfaces/niftyreg/regutils.py index 7c3ed28eaf..182e144676 100644 --- a/nipype/interfaces/niftyreg/regutils.py +++ b/nipype/interfaces/niftyreg/regutils.py @@ -295,6 +295,15 @@ class RegToolsInputSpec(NiftyRegCommandInputSpec): desc=desc, argstr='-smoG %f %f %f') + # Interpolation type + inter_val = traits.Enum( + 'NN', + 'LIN', + 'CUB', + 'SINC', + desc='Interpolation order to use to warp the floating image', + argstr='-interp %d') + class RegToolsOutputSpec(TraitedSpec): """ Output Spec for RegTools. """ From c2e929539d21ef6f196f33facd1581ecacfd4c0e Mon Sep 17 00:00:00 2001 From: Fernando Date: Wed, 28 Feb 2018 18:21:52 +0000 Subject: [PATCH 2/5] Change my affiliation --- .zenodo.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.zenodo.json b/.zenodo.json index 1058e3b150..29e7f047ac 100644 --- a/.zenodo.json +++ b/.zenodo.json @@ -558,7 +558,7 @@ "name": "Flandin, Guillaume" }, { - "affiliation": "Stereotaxy Core, Brain & Spine Institute", + "affiliation": "University College London", "name": "P\u00e9rez-Garc\u00eda, Fernando", "orcid": "0000-0001-9090-3024" }, From d55716ae07777187fa5cc3869b4f4edad33bb098 Mon Sep 17 00:00:00 2001 From: Fernando Date: Wed, 28 Feb 2018 19:57:16 +0000 Subject: [PATCH 3/5] Add _format_arg overload to RegTools NiftyRegCommand --- nipype/interfaces/niftyreg/regutils.py | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/nipype/interfaces/niftyreg/regutils.py b/nipype/interfaces/niftyreg/regutils.py index 182e144676..0b98ee0034 100644 --- a/nipype/interfaces/niftyreg/regutils.py +++ b/nipype/interfaces/niftyreg/regutils.py @@ -335,6 +335,14 @@ class RegTools(NiftyRegCommand): output_spec = RegToolsOutputSpec _suffix = '_tools' + # Need this overload to properly constraint the interpolation type input + def _format_arg(self, name, spec, value): + if name == 'inter_val': + inter_val = {'NN': 0, 'LIN': 1, 'CUB': 3, 'SINC': 5} + return spec.argstr % inter_val[value] + else: + return super(RegTools, self)._format_arg(name, spec, value) + class RegAverageInputSpec(NiftyRegCommandInputSpec): """ Input Spec for RegAverage. """ From 1468583ee01d127e9c67e3971f8c535573493627 Mon Sep 17 00:00:00 2001 From: Fernando Date: Wed, 28 Feb 2018 20:00:01 +0000 Subject: [PATCH 4/5] Fix interp enum value for RegResample and RegTools According to NiftyReg source code: https://cmiclab.cs.ucl.ac.uk/mmodat/niftyreg/blob/master/reg-apps/reg_resample.cpp#L65 --- nipype/interfaces/niftyreg/regutils.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/nipype/interfaces/niftyreg/regutils.py b/nipype/interfaces/niftyreg/regutils.py index 0b98ee0034..0910b7d65c 100644 --- a/nipype/interfaces/niftyreg/regutils.py +++ b/nipype/interfaces/niftyreg/regutils.py @@ -122,7 +122,7 @@ class RegResample(NiftyRegCommand): # Need this overload to properly constraint the interpolation type input def _format_arg(self, name, spec, value): if name == 'inter_val': - inter_val = {'NN': 0, 'LIN': 1, 'CUB': 3, 'SINC': 5} + inter_val = {'NN': 0, 'LIN': 1, 'CUB': 3, 'SINC': 4} return spec.argstr % inter_val[value] else: return super(RegResample, self)._format_arg(name, spec, value) @@ -338,7 +338,7 @@ class RegTools(NiftyRegCommand): # Need this overload to properly constraint the interpolation type input def _format_arg(self, name, spec, value): if name == 'inter_val': - inter_val = {'NN': 0, 'LIN': 1, 'CUB': 3, 'SINC': 5} + inter_val = {'NN': 0, 'LIN': 1, 'CUB': 3, 'SINC': 4} return spec.argstr % inter_val[value] else: return super(RegTools, self)._format_arg(name, spec, value) From e34c6625e799029723c62fe773e856114b6921a4 Mon Sep 17 00:00:00 2001 From: Fernando Date: Wed, 28 Feb 2018 22:56:39 +0000 Subject: [PATCH 5/5] Run make specs for RegTools --- nipype/interfaces/niftyreg/tests/test_auto_RegTools.py | 1 + 1 file changed, 1 insertion(+) diff --git a/nipype/interfaces/niftyreg/tests/test_auto_RegTools.py b/nipype/interfaces/niftyreg/tests/test_auto_RegTools.py index 97ea5e6c92..f0f66083c7 100644 --- a/nipype/interfaces/niftyreg/tests/test_auto_RegTools.py +++ b/nipype/interfaces/niftyreg/tests/test_auto_RegTools.py @@ -24,6 +24,7 @@ def test_RegTools_inputs(): argstr='-in %s', mandatory=True, ), + inter_val=dict(argstr='-interp %d', ), iso_flag=dict(argstr='-iso', ), mask_file=dict(argstr='-nan %s', ), mul_val=dict(argstr='-mul %s', ),