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Merge pull request #2031 from effigies/enh/bbregister_lta
ENH: Add LTA output to BBRegister
2 parents 90cfdd8 + 22dd644 commit cda3fdc

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2 files changed

+17
-1
lines changed

2 files changed

+17
-1
lines changed

nipype/interfaces/freesurfer/preprocess.py

Lines changed: 14 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1155,6 +1155,8 @@ class BBRegisterInputSpec(FSTraitedSpec):
11551155
desc='degrees of freedom for initial registration (FSL)')
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out_fsl_file = traits.Either(traits.Bool, File, argstr="--fslmat %s",
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desc="write the transformation matrix in FSL FLIRT format")
1158+
out_lta_file = traits.Either(traits.Bool, File, argstr="--lta %s", min_ver='5.2.0',
1159+
desc="write the transformation matrix in LTA format")
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registered_file = traits.Either(traits.Bool, File, argstr='--o %s',
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desc='output warped sourcefile either True or filename')
11601162

@@ -1171,6 +1173,7 @@ class BBRegisterInputSpec6(BBRegisterInputSpec):
11711173
class BBRegisterOutputSpec(TraitedSpec):
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out_reg_file = File(exists=True, desc='Output registration file')
11731175
out_fsl_file = File(desc='Output FLIRT-style registration file')
1176+
out_lta_file = File(desc='Output LTA-style registration file')
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min_cost_file = File(exists=True, desc='Output registration minimum cost file')
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registered_file = File(desc='Registered and resampled source file')
11761179

@@ -1219,6 +1222,16 @@ def _list_outputs(self):
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else:
12201223
outputs['registered_file'] = op.abspath(_in.registered_file)
12211224

1225+
if isdefined(_in.out_lta_file):
1226+
if isinstance(_in.out_fsl_file, bool):
1227+
suffix = '_bbreg_%s.lta' % _in.subject_id
1228+
out_lta_file = fname_presuffix(_in.source_file,
1229+
suffix=suffix,
1230+
use_ext=False)
1231+
outputs['out_lta_file'] = out_lta_file
1232+
else:
1233+
outputs['out_lta_file'] = op.abspath(_in.out_lta_file)
1234+
12221235
if isdefined(_in.out_fsl_file):
12231236
if isinstance(_in.out_fsl_file, bool):
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suffix = '_bbreg_%s.mat' % _in.subject_id
@@ -1234,7 +1247,7 @@ def _list_outputs(self):
12341247

12351248
def _format_arg(self, name, spec, value):
12361249

1237-
if name in ['registered_file', 'out_fsl_file']:
1250+
if name in ['registered_file', 'out_fsl_file', 'out_lta_file']:
12381251
if isinstance(value, bool):
12391252
fname = self._list_outputs()[name]
12401253
else:

nipype/interfaces/freesurfer/tests/test_BBRegister.py

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@ def test_BBRegister_inputs():
1515
init_reg_file=dict(argstr='--init-reg %s', mandatory=True, xor=['init'],),
1616
intermediate_file=dict(argstr='--int %s',),
1717
out_fsl_file=dict(argstr='--fslmat %s',),
18+
out_lta_file=dict(argstr='--lta %s', min_ver='5.2.0',),
1819
out_reg_file=dict(argstr='--reg %s', genfile=True,),
1920
reg_frame=dict(argstr='--frame %d', xor=['reg_middle_frame'],),
2021
reg_middle_frame=dict(argstr='--mid-frame', xor=['reg_frame'],),
@@ -37,6 +38,7 @@ def test_BBRegister_inputs():
3738
init_reg_file=dict(argstr='--init-reg %s', xor=['init'],),
3839
intermediate_file=dict(argstr='--int %s',),
3940
out_fsl_file=dict(argstr='--fslmat %s',),
41+
out_lta_file=dict(argstr='--lta %s', min_ver='5.2.0',),
4042
out_reg_file=dict(argstr='--reg %s', genfile=True,),
4143
reg_frame=dict(argstr='--frame %d', xor=['reg_middle_frame'],),
4244
reg_middle_frame=dict(argstr='--mid-frame', xor=['reg_frame'],),
@@ -62,6 +64,7 @@ def test_BBRegister_inputs():
6264
def test_BBRegister_outputs():
6365
output_map = dict(min_cost_file=dict(),
6466
out_fsl_file=dict(),
67+
out_lta_file=dict(),
6568
out_reg_file=dict(),
6669
registered_file=dict(),
6770
)

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