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Merge pull request rust-lang#187 from GuillaumeGomez/invalid-conversion
Prevent invalid intrinsics conversion generation
2 parents 39d7a23 + f7a3dff commit d6aadc6

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3 files changed

+65
-44
lines changed

3 files changed

+65
-44
lines changed

‎src/intrinsic/archs.rs

Lines changed: 44 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -5995,8 +5995,8 @@ match name {
59955995
"llvm.x86.avx512.mask.add.ps.128" => "__builtin_ia32_addps128_mask",
59965996
"llvm.x86.avx512.mask.add.ps.256" => "__builtin_ia32_addps256_mask",
59975997
"llvm.x86.avx512.mask.add.ps.512" => "__builtin_ia32_addps512_mask",
5998-
"llvm.x86.avx512.mask.add.sd.round" => "__builtin_ia32_addsd_round_mask",
5999-
"llvm.x86.avx512.mask.add.ss.round" => "__builtin_ia32_addss_round_mask",
5998+
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.add.sd.round" => "__builtin_ia32_addsd_round_mask",
5999+
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.add.ss.round" => "__builtin_ia32_addss_round_mask",
60006000
"llvm.x86.avx512.mask.and.pd.128" => "__builtin_ia32_andpd128_mask",
60016001
"llvm.x86.avx512.mask.and.pd.256" => "__builtin_ia32_andpd256_mask",
60026002
"llvm.x86.avx512.mask.and.pd.512" => "__builtin_ia32_andpd512_mask",
@@ -6110,8 +6110,8 @@ match name {
61106110
"llvm.x86.avx512.mask.cvtqq2ps.128" => "__builtin_ia32_cvtqq2ps128_mask",
61116111
"llvm.x86.avx512.mask.cvtqq2ps.256" => "__builtin_ia32_cvtqq2ps256_mask",
61126112
"llvm.x86.avx512.mask.cvtqq2ps.512" => "__builtin_ia32_cvtqq2ps512_mask",
6113-
"llvm.x86.avx512.mask.cvtsd2ss.round" => "__builtin_ia32_cvtsd2ss_round_mask",
6114-
"llvm.x86.avx512.mask.cvtss2sd.round" => "__builtin_ia32_cvtss2sd_round_mask",
6113+
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.cvtsd2ss.round" => "__builtin_ia32_cvtsd2ss_round_mask",
6114+
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.cvtss2sd.round" => "__builtin_ia32_cvtss2sd_round_mask",
61156115
"llvm.x86.avx512.mask.cvttpd2dq.128" => "__builtin_ia32_cvttpd2dq128_mask",
61166116
"llvm.x86.avx512.mask.cvttpd2dq.256" => "__builtin_ia32_cvttpd2dq256_mask",
61176117
"llvm.x86.avx512.mask.cvttpd2dq.512" => "__builtin_ia32_cvttpd2dq512_mask",
@@ -6157,8 +6157,8 @@ match name {
61576157
"llvm.x86.avx512.mask.div.ps.128" => "__builtin_ia32_divps_mask",
61586158
"llvm.x86.avx512.mask.div.ps.256" => "__builtin_ia32_divps256_mask",
61596159
"llvm.x86.avx512.mask.div.ps.512" => "__builtin_ia32_divps512_mask",
6160-
"llvm.x86.avx512.mask.div.sd.round" => "__builtin_ia32_divsd_round_mask",
6161-
"llvm.x86.avx512.mask.div.ss.round" => "__builtin_ia32_divss_round_mask",
6160+
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.div.sd.round" => "__builtin_ia32_divsd_round_mask",
6161+
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.div.ss.round" => "__builtin_ia32_divss_round_mask",
61626162
"llvm.x86.avx512.mask.expand.d.128" => "__builtin_ia32_expandsi128_mask",
61636163
"llvm.x86.avx512.mask.expand.d.256" => "__builtin_ia32_expandsi256_mask",
61646164
"llvm.x86.avx512.mask.expand.d.512" => "__builtin_ia32_expandsi512_mask",
@@ -6205,16 +6205,16 @@ match name {
62056205
"llvm.x86.avx512.mask.getexp.ps.128" => "__builtin_ia32_getexpps128_mask",
62066206
"llvm.x86.avx512.mask.getexp.ps.256" => "__builtin_ia32_getexpps256_mask",
62076207
"llvm.x86.avx512.mask.getexp.ps.512" => "__builtin_ia32_getexpps512_mask",
6208-
"llvm.x86.avx512.mask.getexp.sd" => "__builtin_ia32_getexpsd128_round_mask",
6209-
"llvm.x86.avx512.mask.getexp.ss" => "__builtin_ia32_getexpss128_round_mask",
6208+
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.getexp.sd" => "__builtin_ia32_getexpsd128_round_mask",
6209+
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.getexp.ss" => "__builtin_ia32_getexpss128_round_mask",
62106210
"llvm.x86.avx512.mask.getmant.pd.128" => "__builtin_ia32_getmantpd128_mask",
62116211
"llvm.x86.avx512.mask.getmant.pd.256" => "__builtin_ia32_getmantpd256_mask",
62126212
"llvm.x86.avx512.mask.getmant.pd.512" => "__builtin_ia32_getmantpd512_mask",
62136213
"llvm.x86.avx512.mask.getmant.ps.128" => "__builtin_ia32_getmantps128_mask",
62146214
"llvm.x86.avx512.mask.getmant.ps.256" => "__builtin_ia32_getmantps256_mask",
62156215
"llvm.x86.avx512.mask.getmant.ps.512" => "__builtin_ia32_getmantps512_mask",
6216-
"llvm.x86.avx512.mask.getmant.sd" => "__builtin_ia32_getmantsd_round_mask",
6217-
"llvm.x86.avx512.mask.getmant.ss" => "__builtin_ia32_getmantss_round_mask",
6216+
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.getmant.sd" => "__builtin_ia32_getmantsd_round_mask",
6217+
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.getmant.ss" => "__builtin_ia32_getmantss_round_mask",
62186218
"llvm.x86.avx512.mask.insertf32x4.256" => "__builtin_ia32_insertf32x4_256_mask",
62196219
"llvm.x86.avx512.mask.insertf32x4.512" => "__builtin_ia32_insertf32x4_mask",
62206220
"llvm.x86.avx512.mask.insertf32x8.512" => "__builtin_ia32_insertf32x8_mask",
@@ -6239,16 +6239,16 @@ match name {
62396239
"llvm.x86.avx512.mask.max.ps.128" => "__builtin_ia32_maxps_mask",
62406240
"llvm.x86.avx512.mask.max.ps.256" => "__builtin_ia32_maxps256_mask",
62416241
"llvm.x86.avx512.mask.max.ps.512" => "__builtin_ia32_maxps512_mask",
6242-
"llvm.x86.avx512.mask.max.sd.round" => "__builtin_ia32_maxsd_round_mask",
6243-
"llvm.x86.avx512.mask.max.ss.round" => "__builtin_ia32_maxss_round_mask",
6242+
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.max.sd.round" => "__builtin_ia32_maxsd_round_mask",
6243+
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.max.ss.round" => "__builtin_ia32_maxss_round_mask",
62446244
"llvm.x86.avx512.mask.min.pd.128" => "__builtin_ia32_minpd_mask",
62456245
"llvm.x86.avx512.mask.min.pd.256" => "__builtin_ia32_minpd256_mask",
62466246
"llvm.x86.avx512.mask.min.pd.512" => "__builtin_ia32_minpd512_mask",
62476247
"llvm.x86.avx512.mask.min.ps.128" => "__builtin_ia32_minps_mask",
62486248
"llvm.x86.avx512.mask.min.ps.256" => "__builtin_ia32_minps256_mask",
62496249
"llvm.x86.avx512.mask.min.ps.512" => "__builtin_ia32_minps512_mask",
6250-
"llvm.x86.avx512.mask.min.sd.round" => "__builtin_ia32_minsd_round_mask",
6251-
"llvm.x86.avx512.mask.min.ss.round" => "__builtin_ia32_minss_round_mask",
6250+
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.min.sd.round" => "__builtin_ia32_minsd_round_mask",
6251+
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.min.ss.round" => "__builtin_ia32_minss_round_mask",
62526252
"llvm.x86.avx512.mask.move.sd" => "__builtin_ia32_movsd_mask",
62536253
"llvm.x86.avx512.mask.move.ss" => "__builtin_ia32_movss_mask",
62546254
"llvm.x86.avx512.mask.mul.pd.128" => "__builtin_ia32_mulpd_mask",
@@ -6257,8 +6257,8 @@ match name {
62576257
"llvm.x86.avx512.mask.mul.ps.128" => "__builtin_ia32_mulps_mask",
62586258
"llvm.x86.avx512.mask.mul.ps.256" => "__builtin_ia32_mulps256_mask",
62596259
"llvm.x86.avx512.mask.mul.ps.512" => "__builtin_ia32_mulps512_mask",
6260-
"llvm.x86.avx512.mask.mul.sd.round" => "__builtin_ia32_mulsd_round_mask",
6261-
"llvm.x86.avx512.mask.mul.ss.round" => "__builtin_ia32_mulss_round_mask",
6260+
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.mul.sd.round" => "__builtin_ia32_mulsd_round_mask",
6261+
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.mul.ss.round" => "__builtin_ia32_mulss_round_mask",
62626262
"llvm.x86.avx512.mask.or.pd.128" => "__builtin_ia32_orpd128_mask",
62636263
"llvm.x86.avx512.mask.or.pd.256" => "__builtin_ia32_orpd256_mask",
62646264
"llvm.x86.avx512.mask.or.pd.512" => "__builtin_ia32_orpd512_mask",
@@ -6743,8 +6743,8 @@ match name {
67436743
"llvm.x86.avx512.mask.range.ps.128" => "__builtin_ia32_rangeps128_mask",
67446744
"llvm.x86.avx512.mask.range.ps.256" => "__builtin_ia32_rangeps256_mask",
67456745
"llvm.x86.avx512.mask.range.ps.512" => "__builtin_ia32_rangeps512_mask",
6746-
"llvm.x86.avx512.mask.range.sd" => "__builtin_ia32_rangesd128_round_mask",
6747-
"llvm.x86.avx512.mask.range.ss" => "__builtin_ia32_rangess128_round_mask",
6746+
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.range.sd" => "__builtin_ia32_rangesd128_round_mask",
6747+
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.range.ss" => "__builtin_ia32_rangess128_round_mask",
67486748
"llvm.x86.avx512.mask.reduce.pd.128" => "__builtin_ia32_reducepd128_mask",
67496749
"llvm.x86.avx512.mask.reduce.pd.256" => "__builtin_ia32_reducepd256_mask",
67506750
"llvm.x86.avx512.mask.reduce.pd.512" => "__builtin_ia32_reducepd512_mask",
@@ -6759,16 +6759,16 @@ match name {
67596759
"llvm.x86.avx512.mask.rndscale.ps.128" => "__builtin_ia32_rndscaleps_128_mask",
67606760
"llvm.x86.avx512.mask.rndscale.ps.256" => "__builtin_ia32_rndscaleps_256_mask",
67616761
"llvm.x86.avx512.mask.rndscale.ps.512" => "__builtin_ia32_rndscaleps_mask",
6762-
"llvm.x86.avx512.mask.rndscale.sd" => "__builtin_ia32_rndscalesd_round_mask",
6763-
"llvm.x86.avx512.mask.rndscale.ss" => "__builtin_ia32_rndscaless_round_mask",
6762+
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.rndscale.sd" => "__builtin_ia32_rndscalesd_round_mask",
6763+
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.rndscale.ss" => "__builtin_ia32_rndscaless_round_mask",
67646764
"llvm.x86.avx512.mask.scalef.pd.128" => "__builtin_ia32_scalefpd128_mask",
67656765
"llvm.x86.avx512.mask.scalef.pd.256" => "__builtin_ia32_scalefpd256_mask",
67666766
"llvm.x86.avx512.mask.scalef.pd.512" => "__builtin_ia32_scalefpd512_mask",
67676767
"llvm.x86.avx512.mask.scalef.ps.128" => "__builtin_ia32_scalefps128_mask",
67686768
"llvm.x86.avx512.mask.scalef.ps.256" => "__builtin_ia32_scalefps256_mask",
67696769
"llvm.x86.avx512.mask.scalef.ps.512" => "__builtin_ia32_scalefps512_mask",
6770-
"llvm.x86.avx512.mask.scalef.sd" => "__builtin_ia32_scalefsd_round_mask",
6771-
"llvm.x86.avx512.mask.scalef.ss" => "__builtin_ia32_scalefss_round_mask",
6770+
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.scalef.sd" => "__builtin_ia32_scalefsd_round_mask",
6771+
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.scalef.ss" => "__builtin_ia32_scalefss_round_mask",
67726772
"llvm.x86.avx512.mask.shuf.f32x4" => "__builtin_ia32_shuf_f32x4_mask",
67736773
"llvm.x86.avx512.mask.shuf.f32x4.256" => "__builtin_ia32_shuf_f32x4_256_mask",
67746774
"llvm.x86.avx512.mask.shuf.f64x2" => "__builtin_ia32_shuf_f64x2_mask",
@@ -6789,8 +6789,8 @@ match name {
67896789
"llvm.x86.avx512.mask.sqrt.ps.128" => "__builtin_ia32_sqrtps128_mask",
67906790
"llvm.x86.avx512.mask.sqrt.ps.256" => "__builtin_ia32_sqrtps256_mask",
67916791
"llvm.x86.avx512.mask.sqrt.ps.512" => "__builtin_ia32_sqrtps512_mask",
6792-
"llvm.x86.avx512.mask.sqrt.sd" => "__builtin_ia32_sqrtsd_round_mask",
6793-
"llvm.x86.avx512.mask.sqrt.ss" => "__builtin_ia32_sqrtss_round_mask",
6792+
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.sqrt.sd" => "__builtin_ia32_sqrtsd_round_mask",
6793+
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.sqrt.ss" => "__builtin_ia32_sqrtss_round_mask",
67946794
"llvm.x86.avx512.mask.store.ss" => "__builtin_ia32_storess_mask",
67956795
"llvm.x86.avx512.mask.storeu.d.512" => "__builtin_ia32_storedqusi512_mask",
67966796
"llvm.x86.avx512.mask.storeu.pd.512" => "__builtin_ia32_storeupd512_mask",
@@ -6802,8 +6802,8 @@ match name {
68026802
"llvm.x86.avx512.mask.sub.ps.128" => "__builtin_ia32_subps128_mask",
68036803
"llvm.x86.avx512.mask.sub.ps.256" => "__builtin_ia32_subps256_mask",
68046804
"llvm.x86.avx512.mask.sub.ps.512" => "__builtin_ia32_subps512_mask",
6805-
"llvm.x86.avx512.mask.sub.sd.round" => "__builtin_ia32_subsd_round_mask",
6806-
"llvm.x86.avx512.mask.sub.ss.round" => "__builtin_ia32_subss_round_mask",
6805+
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.sub.sd.round" => "__builtin_ia32_subsd_round_mask",
6806+
// [INVALID CONVERSION]: "llvm.x86.avx512.mask.sub.ss.round" => "__builtin_ia32_subss_round_mask",
68076807
"llvm.x86.avx512.mask.valign.d.128" => "__builtin_ia32_alignd128_mask",
68086808
"llvm.x86.avx512.mask.valign.d.256" => "__builtin_ia32_alignd256_mask",
68096809
"llvm.x86.avx512.mask.valign.d.512" => "__builtin_ia32_alignd512_mask",
@@ -7121,9 +7121,9 @@ match name {
71217121
"llvm.x86.avx512.rcp14.ss" => "__builtin_ia32_rcp14ss_mask",
71227122
"llvm.x86.avx512.rcp28.pd" => "__builtin_ia32_rcp28pd_mask",
71237123
"llvm.x86.avx512.rcp28.ps" => "__builtin_ia32_rcp28ps_mask",
7124-
"llvm.x86.avx512.rcp28.sd" => "__builtin_ia32_rcp28sd_round_mask",
7124+
// [INVALID CONVERSION]: "llvm.x86.avx512.rcp28.sd" => "__builtin_ia32_rcp28sd_round_mask",
71257125
// [DUPLICATE]: "llvm.x86.avx512.rcp28.sd" => "__builtin_ia32_rcp28sd_mask",
7126-
"llvm.x86.avx512.rcp28.ss" => "__builtin_ia32_rcp28ss_round_mask",
7126+
// [INVALID CONVERSION]: "llvm.x86.avx512.rcp28.ss" => "__builtin_ia32_rcp28ss_round_mask",
71277127
// [DUPLICATE]: "llvm.x86.avx512.rcp28.ss" => "__builtin_ia32_rcp28ss_mask",
71287128
"llvm.x86.avx512.rndscale.sd" => "__builtin_ia32_rndscalesd",
71297129
"llvm.x86.avx512.rndscale.ss" => "__builtin_ia32_rndscaless",
@@ -7137,9 +7137,9 @@ match name {
71377137
"llvm.x86.avx512.rsqrt14.ss" => "__builtin_ia32_rsqrt14ss_mask",
71387138
"llvm.x86.avx512.rsqrt28.pd" => "__builtin_ia32_rsqrt28pd_mask",
71397139
"llvm.x86.avx512.rsqrt28.ps" => "__builtin_ia32_rsqrt28ps_mask",
7140-
"llvm.x86.avx512.rsqrt28.sd" => "__builtin_ia32_rsqrt28sd_round_mask",
7140+
// [INVALID CONVERSION]: "llvm.x86.avx512.rsqrt28.sd" => "__builtin_ia32_rsqrt28sd_round_mask",
71417141
// [DUPLICATE]: "llvm.x86.avx512.rsqrt28.sd" => "__builtin_ia32_rsqrt28sd_mask",
7142-
"llvm.x86.avx512.rsqrt28.ss" => "__builtin_ia32_rsqrt28ss_round_mask",
7142+
// [INVALID CONVERSION]: "llvm.x86.avx512.rsqrt28.ss" => "__builtin_ia32_rsqrt28ss_round_mask",
71437143
// [DUPLICATE]: "llvm.x86.avx512.rsqrt28.ss" => "__builtin_ia32_rsqrt28ss_mask",
71447144
"llvm.x86.avx512.scatter.dpd.512" => "__builtin_ia32_scattersiv8df",
71457145
"llvm.x86.avx512.scatter.dpi.512" => "__builtin_ia32_scattersiv16si",
@@ -7237,21 +7237,21 @@ match name {
72377237
"llvm.x86.avx512bf16.dpbf16ps.512" => "__builtin_ia32_dpbf16ps_512",
72387238
"llvm.x86.avx512fp16.add.ph.512" => "__builtin_ia32_addph512",
72397239
"llvm.x86.avx512fp16.div.ph.512" => "__builtin_ia32_divph512",
7240-
"llvm.x86.avx512fp16.mask.add.sh.round" => "__builtin_ia32_addsh_round_mask",
7240+
// [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.add.sh.round" => "__builtin_ia32_addsh_round_mask",
72417241
"llvm.x86.avx512fp16.mask.cmp.sh" => "__builtin_ia32_cmpsh_mask",
7242-
"llvm.x86.avx512fp16.mask.div.sh.round" => "__builtin_ia32_divsh_round_mask",
7242+
// [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.div.sh.round" => "__builtin_ia32_divsh_round_mask",
72437243
"llvm.x86.avx512fp16.mask.fpclass.sh" => "__builtin_ia32_fpclasssh_mask",
72447244
"llvm.x86.avx512fp16.mask.getexp.ph.128" => "__builtin_ia32_getexpph128_mask",
72457245
"llvm.x86.avx512fp16.mask.getexp.ph.256" => "__builtin_ia32_getexpph256_mask",
72467246
"llvm.x86.avx512fp16.mask.getexp.ph.512" => "__builtin_ia32_getexpph512_mask",
7247-
"llvm.x86.avx512fp16.mask.getexp.sh" => "__builtin_ia32_getexpsh128_round_mask",
7247+
// [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.getexp.sh" => "__builtin_ia32_getexpsh128_round_mask",
72487248
"llvm.x86.avx512fp16.mask.getmant.ph.128" => "__builtin_ia32_getmantph128_mask",
72497249
"llvm.x86.avx512fp16.mask.getmant.ph.256" => "__builtin_ia32_getmantph256_mask",
72507250
"llvm.x86.avx512fp16.mask.getmant.ph.512" => "__builtin_ia32_getmantph512_mask",
7251-
"llvm.x86.avx512fp16.mask.getmant.sh" => "__builtin_ia32_getmantsh_round_mask",
7252-
"llvm.x86.avx512fp16.mask.max.sh.round" => "__builtin_ia32_maxsh_round_mask",
7253-
"llvm.x86.avx512fp16.mask.min.sh.round" => "__builtin_ia32_minsh_round_mask",
7254-
"llvm.x86.avx512fp16.mask.mul.sh.round" => "__builtin_ia32_mulsh_round_mask",
7251+
// [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.getmant.sh" => "__builtin_ia32_getmantsh_round_mask",
7252+
// [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.max.sh.round" => "__builtin_ia32_maxsh_round_mask",
7253+
// [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.min.sh.round" => "__builtin_ia32_minsh_round_mask",
7254+
// [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.mul.sh.round" => "__builtin_ia32_mulsh_round_mask",
72557255
"llvm.x86.avx512fp16.mask.rcp.ph.128" => "__builtin_ia32_rcpph128_mask",
72567256
"llvm.x86.avx512fp16.mask.rcp.ph.256" => "__builtin_ia32_rcpph256_mask",
72577257
"llvm.x86.avx512fp16.mask.rcp.ph.512" => "__builtin_ia32_rcpph512_mask",
@@ -7263,16 +7263,16 @@ match name {
72637263
"llvm.x86.avx512fp16.mask.rndscale.ph.128" => "__builtin_ia32_rndscaleph_128_mask",
72647264
"llvm.x86.avx512fp16.mask.rndscale.ph.256" => "__builtin_ia32_rndscaleph_256_mask",
72657265
"llvm.x86.avx512fp16.mask.rndscale.ph.512" => "__builtin_ia32_rndscaleph_mask",
7266-
"llvm.x86.avx512fp16.mask.rndscale.sh" => "__builtin_ia32_rndscalesh_round_mask",
7266+
// [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.rndscale.sh" => "__builtin_ia32_rndscalesh_round_mask",
72677267
"llvm.x86.avx512fp16.mask.rsqrt.ph.128" => "__builtin_ia32_rsqrtph128_mask",
72687268
"llvm.x86.avx512fp16.mask.rsqrt.ph.256" => "__builtin_ia32_rsqrtph256_mask",
72697269
"llvm.x86.avx512fp16.mask.rsqrt.ph.512" => "__builtin_ia32_rsqrtph512_mask",
72707270
"llvm.x86.avx512fp16.mask.rsqrt.sh" => "__builtin_ia32_rsqrtsh_mask",
72717271
"llvm.x86.avx512fp16.mask.scalef.ph.128" => "__builtin_ia32_scalefph128_mask",
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"llvm.x86.avx512fp16.mask.scalef.ph.256" => "__builtin_ia32_scalefph256_mask",
72737273
"llvm.x86.avx512fp16.mask.scalef.ph.512" => "__builtin_ia32_scalefph512_mask",
7274-
"llvm.x86.avx512fp16.mask.scalef.sh" => "__builtin_ia32_scalefsh_round_mask",
7275-
"llvm.x86.avx512fp16.mask.sub.sh.round" => "__builtin_ia32_subsh_round_mask",
7274+
// [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.scalef.sh" => "__builtin_ia32_scalefsh_round_mask",
7275+
// [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.sub.sh.round" => "__builtin_ia32_subsh_round_mask",
72767276
"llvm.x86.avx512fp16.mask.vcvtdq2ph.128" => "__builtin_ia32_vcvtdq2ph128_mask",
72777277
"llvm.x86.avx512fp16.mask.vcvtpd2ph.128" => "__builtin_ia32_vcvtpd2ph128_mask",
72787278
"llvm.x86.avx512fp16.mask.vcvtpd2ph.256" => "__builtin_ia32_vcvtpd2ph256_mask",
@@ -7306,10 +7306,10 @@ match name {
73067306
"llvm.x86.avx512fp16.mask.vcvtps2phx.512" => "__builtin_ia32_vcvtps2phx512_mask",
73077307
"llvm.x86.avx512fp16.mask.vcvtqq2ph.128" => "__builtin_ia32_vcvtqq2ph128_mask",
73087308
"llvm.x86.avx512fp16.mask.vcvtqq2ph.256" => "__builtin_ia32_vcvtqq2ph256_mask",
7309-
"llvm.x86.avx512fp16.mask.vcvtsd2sh.round" => "__builtin_ia32_vcvtsd2sh_round_mask",
7310-
"llvm.x86.avx512fp16.mask.vcvtsh2sd.round" => "__builtin_ia32_vcvtsh2sd_round_mask",
7311-
"llvm.x86.avx512fp16.mask.vcvtsh2ss.round" => "__builtin_ia32_vcvtsh2ss_round_mask",
7312-
"llvm.x86.avx512fp16.mask.vcvtss2sh.round" => "__builtin_ia32_vcvtss2sh_round_mask",
7309+
// [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.vcvtsd2sh.round" => "__builtin_ia32_vcvtsd2sh_round_mask",
7310+
// [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.vcvtsh2sd.round" => "__builtin_ia32_vcvtsh2sd_round_mask",
7311+
// [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.vcvtsh2ss.round" => "__builtin_ia32_vcvtsh2ss_round_mask",
7312+
// [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.vcvtss2sh.round" => "__builtin_ia32_vcvtss2sh_round_mask",
73137313
"llvm.x86.avx512fp16.mask.vcvttph2dq.128" => "__builtin_ia32_vcvttph2dq128_mask",
73147314
"llvm.x86.avx512fp16.mask.vcvttph2dq.256" => "__builtin_ia32_vcvttph2dq256_mask",
73157315
"llvm.x86.avx512fp16.mask.vcvttph2dq.512" => "__builtin_ia32_vcvttph2dq512_mask",

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