From c7318a00a232036da68efd30072fa041e3b1aaed Mon Sep 17 00:00:00 2001 From: Alexandros Lamprineas Date: Wed, 28 May 2025 15:10:20 +0100 Subject: [PATCH] [Clang][FMV] Stop emitting implicit default version using target_clones. With the current behavior the following example yields a linker error: "multiple definition of `foo.default'" // Translation Unit 1 __attribute__((target_clones("dotprod, sve"))) int foo(void) { return 1; } // Translation Unit 2 int foo(void) { return 0; } __attribute__((target_version("dotprod"))) int foo(void); __attribute__((target_version("sve"))) int foo(void); int bar(void) { return foo(); } That is because foo.default is generated twice. As a user I don't find this particularly intuitive. If I wanted the default to be generated in TU1 I'd rather write target_clones("dotprod, sve", "default") explicitly. When changing the code I noticed that the RISC-V target defers the resolver emission when encountering a target_version definition. This seems accidental since it only makes sense for AArch64, where we only emit a resolver once we've processed the entire TU, and only if the default version is present. I've changed this so that RISC-V immediately emmits the resolver. I adjusted the codegen tests since the functions now appear in a different order. Implements https://github.com/ARM-software/acle/pull/377 --- clang/lib/CodeGen/CodeGenModule.cpp | 25 +- clang/lib/Sema/SemaDeclAttr.cpp | 8 +- clang/test/AST/attr-target-version.c | 2 +- clang/test/CodeGen/AArch64/fmv-detection.c | 776 +++++++++--------- .../AArch64/fmv-duplicate-mangled-name.c | 24 + clang/test/CodeGen/AArch64/fmv-features.c | 2 +- .../CodeGen/AArch64/fmv-resolver-emission.c | 44 + .../CodeGen/AArch64/mixed-target-attributes.c | 172 ++-- .../test/CodeGen/attr-target-clones-aarch64.c | 574 +++++-------- .../test/CodeGen/attr-target-version-riscv.c | 314 +++---- .../CodeGenCXX/attr-target-clones-aarch64.cpp | 109 +-- .../CodeGenCXX/attr-target-version-riscv.cpp | 298 +++---- clang/test/Sema/attr-target-clones-aarch64.c | 2 + 13 files changed, 1112 insertions(+), 1238 deletions(-) create mode 100644 clang/test/CodeGen/AArch64/fmv-duplicate-mangled-name.c diff --git a/clang/lib/CodeGen/CodeGenModule.cpp b/clang/lib/CodeGen/CodeGenModule.cpp index 6d2c705338ecf..9383c57d3c991 100644 --- a/clang/lib/CodeGen/CodeGenModule.cpp +++ b/clang/lib/CodeGen/CodeGenModule.cpp @@ -4237,19 +4237,19 @@ void CodeGenModule::EmitMultiVersionFunctionDefinition(GlobalDecl GD, EmitGlobalFunctionDefinition(GD.getWithMultiVersionIndex(I), nullptr); } else if (auto *TC = FD->getAttr()) { for (unsigned I = 0; I < TC->featuresStrs_size(); ++I) - // AArch64 favors the default target version over the clone if any. - if ((!TC->isDefaultVersion(I) || !getTarget().getTriple().isAArch64()) && - TC->isFirstOfVersion(I)) + if (TC->isFirstOfVersion(I)) EmitGlobalFunctionDefinition(GD.getWithMultiVersionIndex(I), nullptr); - // Ensure that the resolver function is also emitted. - GetOrCreateMultiVersionResolver(GD); } else EmitGlobalFunctionDefinition(GD, GV); - // Defer the resolver emission until we can reason whether the TU - // contains a default target version implementation. - if (FD->isTargetVersionMultiVersion()) - AddDeferredMultiVersionResolverToEmit(GD); + // Ensure that the resolver function is also emitted. + if (FD->isTargetVersionMultiVersion() || FD->isTargetClonesMultiVersion()) { + // On AArch64 defer the resolver emission until the entire TU is processed. + if (getTarget().getTriple().isAArch64()) + AddDeferredMultiVersionResolverToEmit(GD); + else + GetOrCreateMultiVersionResolver(GD); + } } void CodeGenModule::EmitGlobalDefinition(GlobalDecl GD, llvm::GlobalValue *GV) { @@ -4351,7 +4351,7 @@ void CodeGenModule::emitMultiVersionFunctions() { }; // For AArch64, a resolver is only emitted if a function marked with - // target_version("default")) or target_clones() is present and defined + // target_version("default")) or target_clones("default") is defined // in this TU. For other architectures it is always emitted. bool ShouldEmitResolver = !getTarget().getTriple().isAArch64(); SmallVector Options; @@ -4374,12 +4374,11 @@ void CodeGenModule::emitMultiVersionFunctions() { TVA->getFeatures(Feats, Delim); Options.emplace_back(Func, Feats); } else if (const auto *TC = CurFD->getAttr()) { - if (IsDefined) - ShouldEmitResolver = true; for (unsigned I = 0; I < TC->featuresStrs_size(); ++I) { if (!TC->isFirstOfVersion(I)) continue; - + if (TC->isDefaultVersion(I) && IsDefined) + ShouldEmitResolver = true; llvm::Function *Func = createFunction(CurFD, I); Feats.clear(); if (getTarget().getTriple().isX86()) { diff --git a/clang/lib/Sema/SemaDeclAttr.cpp b/clang/lib/Sema/SemaDeclAttr.cpp index 54bac40982eda..6a202f5c6c167 100644 --- a/clang/lib/Sema/SemaDeclAttr.cpp +++ b/clang/lib/Sema/SemaDeclAttr.cpp @@ -3494,13 +3494,7 @@ static void handleTargetClonesAttr(Sema &S, Decl *D, const ParsedAttr &AL) { if (HasCommas && AL.getNumArgs() > 1) S.Diag(AL.getLoc(), diag::warn_target_clone_mixed_values); - if (S.Context.getTargetInfo().getTriple().isAArch64() && !HasDefault) { - // Add default attribute if there is no one - HasDefault = true; - Strings.push_back("default"); - } - - if (!HasDefault) { + if (!HasDefault && !S.Context.getTargetInfo().getTriple().isAArch64()) { S.Diag(AL.getLoc(), diag::err_target_clone_must_have_default); return; } diff --git a/clang/test/AST/attr-target-version.c b/clang/test/AST/attr-target-version.c index 52ac0e61b5a59..b537f5e685a31 100644 --- a/clang/test/AST/attr-target-version.c +++ b/clang/test/AST/attr-target-version.c @@ -1,7 +1,7 @@ // RUN: %clang_cc1 -triple aarch64-linux-gnu -ast-dump %s | FileCheck %s int __attribute__((target_version("sve2-bitperm + sha2"))) foov(void) { return 1; } -int __attribute__((target_clones(" lse + fp + sha3 "))) fooc(void) { return 2; } +int __attribute__((target_clones(" lse + fp + sha3 ", "default"))) fooc(void) { return 2; } // CHECK: TargetVersionAttr // CHECK: sve2-bitperm + sha2 // CHECK: TargetClonesAttr diff --git a/clang/test/CodeGen/AArch64/fmv-detection.c b/clang/test/CodeGen/AArch64/fmv-detection.c index 44702a04e532e..e585140a1eb08 100644 --- a/clang/test/CodeGen/AArch64/fmv-detection.c +++ b/clang/test/CodeGen/AArch64/fmv-detection.c @@ -97,7 +97,7 @@ __attribute__((target_version("wfxt"))) int fmv(void) { return 0; } __attribute__((target_version("cssc+fp"))) int fmv(void); -__attribute__((target_version("default"))) int fmv(void); +__attribute__((target_version("default"))) int fmv(void) { return 0; } int caller() { return fmv(); @@ -121,380 +121,6 @@ int caller() { // CHECK-NEXT: ret i32 0 // // -// CHECK-LABEL: define {{[^@]+}}@fmv.resolver() comdat { -// CHECK-NEXT: resolver_entry: -// CHECK-NEXT: call void @__init_cpu_features_resolver() -// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 2304 -// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 2304 -// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] -// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] -// CHECK: resolver_return: -// CHECK-NEXT: ret ptr @fmv._McsscMfp -// CHECK: resolver_else: -// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 2048 -// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 2048 -// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] -// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] -// CHECK: resolver_return1: -// CHECK-NEXT: ret ptr @fmv._Mcssc -// CHECK: resolver_else2: -// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 576460752303423488 -// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 576460752303423488 -// CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]] -// CHECK-NEXT: br i1 [[TMP11]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]] -// CHECK: resolver_return3: -// CHECK-NEXT: ret ptr @fmv._Mmops -// CHECK: resolver_else4: -// CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP13:%.*]] = and i64 [[TMP12]], 144119586256651008 -// CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[TMP13]], 144119586256651008 -// CHECK-NEXT: [[TMP15:%.*]] = and i1 true, [[TMP14]] -// CHECK-NEXT: br i1 [[TMP15]], label [[RESOLVER_RETURN5:%.*]], label [[RESOLVER_ELSE6:%.*]] -// CHECK: resolver_return5: -// CHECK-NEXT: ret ptr @fmv._Msme2 -// CHECK: resolver_else6: -// CHECK-NEXT: [[TMP16:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP17:%.*]] = and i64 [[TMP16]], 72061992218723072 -// CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[TMP17]], 72061992218723072 -// CHECK-NEXT: [[TMP19:%.*]] = and i1 true, [[TMP18]] -// CHECK-NEXT: br i1 [[TMP19]], label [[RESOLVER_RETURN7:%.*]], label [[RESOLVER_ELSE8:%.*]] -// CHECK: resolver_return7: -// CHECK-NEXT: ret ptr @fmv._Msme-i16i64 -// CHECK: resolver_else8: -// CHECK-NEXT: [[TMP20:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP21:%.*]] = and i64 [[TMP20]], 36033195199759104 -// CHECK-NEXT: [[TMP22:%.*]] = icmp eq i64 [[TMP21]], 36033195199759104 -// CHECK-NEXT: [[TMP23:%.*]] = and i1 true, [[TMP22]] -// CHECK-NEXT: br i1 [[TMP23]], label [[RESOLVER_RETURN9:%.*]], label [[RESOLVER_ELSE10:%.*]] -// CHECK: resolver_return9: -// CHECK-NEXT: ret ptr @fmv._Msme-f64f64 -// CHECK: resolver_else10: -// CHECK-NEXT: [[TMP24:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP25:%.*]] = and i64 [[TMP24]], 18014398509481984 -// CHECK-NEXT: [[TMP26:%.*]] = icmp eq i64 [[TMP25]], 18014398509481984 -// CHECK-NEXT: [[TMP27:%.*]] = and i1 true, [[TMP26]] -// CHECK-NEXT: br i1 [[TMP27]], label [[RESOLVER_RETURN11:%.*]], label [[RESOLVER_ELSE12:%.*]] -// CHECK: resolver_return11: -// CHECK-NEXT: ret ptr @fmv._Mwfxt -// CHECK: resolver_else12: -// CHECK-NEXT: [[TMP28:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP29:%.*]] = and i64 [[TMP28]], 1125899906842624 -// CHECK-NEXT: [[TMP30:%.*]] = icmp eq i64 [[TMP29]], 1125899906842624 -// CHECK-NEXT: [[TMP31:%.*]] = and i1 true, [[TMP30]] -// CHECK-NEXT: br i1 [[TMP31]], label [[RESOLVER_RETURN13:%.*]], label [[RESOLVER_ELSE14:%.*]] -// CHECK: resolver_return13: -// CHECK-NEXT: ret ptr @fmv._Mbti -// CHECK: resolver_else14: -// CHECK-NEXT: [[TMP32:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP33:%.*]] = and i64 [[TMP32]], 562949953421312 -// CHECK-NEXT: [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 562949953421312 -// CHECK-NEXT: [[TMP35:%.*]] = and i1 true, [[TMP34]] -// CHECK-NEXT: br i1 [[TMP35]], label [[RESOLVER_RETURN15:%.*]], label [[RESOLVER_ELSE16:%.*]] -// CHECK: resolver_return15: -// CHECK-NEXT: ret ptr @fmv._Mssbs -// CHECK: resolver_else16: -// CHECK-NEXT: [[TMP36:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP37:%.*]] = and i64 [[TMP36]], 70368744177664 -// CHECK-NEXT: [[TMP38:%.*]] = icmp eq i64 [[TMP37]], 70368744177664 -// CHECK-NEXT: [[TMP39:%.*]] = and i1 true, [[TMP38]] -// CHECK-NEXT: br i1 [[TMP39]], label [[RESOLVER_RETURN17:%.*]], label [[RESOLVER_ELSE18:%.*]] -// CHECK: resolver_return17: -// CHECK-NEXT: ret ptr @fmv._Msb -// CHECK: resolver_else18: -// CHECK-NEXT: [[TMP40:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP41:%.*]] = and i64 [[TMP40]], 17592186044416 -// CHECK-NEXT: [[TMP42:%.*]] = icmp eq i64 [[TMP41]], 17592186044416 -// CHECK-NEXT: [[TMP43:%.*]] = and i1 true, [[TMP42]] -// CHECK-NEXT: br i1 [[TMP43]], label [[RESOLVER_RETURN19:%.*]], label [[RESOLVER_ELSE20:%.*]] -// CHECK: resolver_return19: -// CHECK-NEXT: ret ptr @fmv._Mmemtag -// CHECK: resolver_else20: -// CHECK-NEXT: [[TMP44:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP45:%.*]] = and i64 [[TMP44]], 4398180795136 -// CHECK-NEXT: [[TMP46:%.*]] = icmp eq i64 [[TMP45]], 4398180795136 -// CHECK-NEXT: [[TMP47:%.*]] = and i1 true, [[TMP46]] -// CHECK-NEXT: br i1 [[TMP47]], label [[RESOLVER_RETURN21:%.*]], label [[RESOLVER_ELSE22:%.*]] -// CHECK: resolver_return21: -// CHECK-NEXT: ret ptr @fmv._Msme -// CHECK: resolver_else22: -// CHECK-NEXT: [[TMP48:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP49:%.*]] = and i64 [[TMP48]], 2268816540448 -// CHECK-NEXT: [[TMP50:%.*]] = icmp eq i64 [[TMP49]], 2268816540448 -// CHECK-NEXT: [[TMP51:%.*]] = and i1 true, [[TMP50]] -// CHECK-NEXT: br i1 [[TMP51]], label [[RESOLVER_RETURN23:%.*]], label [[RESOLVER_ELSE24:%.*]] -// CHECK: resolver_return23: -// CHECK-NEXT: ret ptr @fmv._Msve2-sm4 -// CHECK: resolver_else24: -// CHECK-NEXT: [[TMP52:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP53:%.*]] = and i64 [[TMP52]], 1169304924928 -// CHECK-NEXT: [[TMP54:%.*]] = icmp eq i64 [[TMP53]], 1169304924928 -// CHECK-NEXT: [[TMP55:%.*]] = and i1 true, [[TMP54]] -// CHECK-NEXT: br i1 [[TMP55]], label [[RESOLVER_RETURN25:%.*]], label [[RESOLVER_ELSE26:%.*]] -// CHECK: resolver_return25: -// CHECK-NEXT: ret ptr @fmv._Msve2-sha3 -// CHECK: resolver_else26: -// CHECK-NEXT: [[TMP56:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP57:%.*]] = and i64 [[TMP56]], 619549098240 -// CHECK-NEXT: [[TMP58:%.*]] = icmp eq i64 [[TMP57]], 619549098240 -// CHECK-NEXT: [[TMP59:%.*]] = and i1 true, [[TMP58]] -// CHECK-NEXT: br i1 [[TMP59]], label [[RESOLVER_RETURN27:%.*]], label [[RESOLVER_ELSE28:%.*]] -// CHECK: resolver_return27: -// CHECK-NEXT: ret ptr @fmv._Msve2-bitperm -// CHECK: resolver_else28: -// CHECK-NEXT: [[TMP60:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP61:%.*]] = and i64 [[TMP60]], 344671224576 -// CHECK-NEXT: [[TMP62:%.*]] = icmp eq i64 [[TMP61]], 344671224576 -// CHECK-NEXT: [[TMP63:%.*]] = and i1 true, [[TMP62]] -// CHECK-NEXT: br i1 [[TMP63]], label [[RESOLVER_RETURN29:%.*]], label [[RESOLVER_ELSE30:%.*]] -// CHECK: resolver_return29: -// CHECK-NEXT: ret ptr @fmv._Msve2-aes -// CHECK: resolver_else30: -// CHECK-NEXT: [[TMP64:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP65:%.*]] = and i64 [[TMP64]], 69793284352 -// CHECK-NEXT: [[TMP66:%.*]] = icmp eq i64 [[TMP65]], 69793284352 -// CHECK-NEXT: [[TMP67:%.*]] = and i1 true, [[TMP66]] -// CHECK-NEXT: br i1 [[TMP67]], label [[RESOLVER_RETURN31:%.*]], label [[RESOLVER_ELSE32:%.*]] -// CHECK: resolver_return31: -// CHECK-NEXT: ret ptr @fmv._Msve2 -// CHECK: resolver_else32: -// CHECK-NEXT: [[TMP68:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP69:%.*]] = and i64 [[TMP68]], 35433545984 -// CHECK-NEXT: [[TMP70:%.*]] = icmp eq i64 [[TMP69]], 35433545984 -// CHECK-NEXT: [[TMP71:%.*]] = and i1 true, [[TMP70]] -// CHECK-NEXT: br i1 [[TMP71]], label [[RESOLVER_RETURN33:%.*]], label [[RESOLVER_ELSE34:%.*]] -// CHECK: resolver_return33: -// CHECK-NEXT: ret ptr @fmv._Mf64mm -// CHECK: resolver_else34: -// CHECK-NEXT: [[TMP72:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP73:%.*]] = and i64 [[TMP72]], 18253676800 -// CHECK-NEXT: [[TMP74:%.*]] = icmp eq i64 [[TMP73]], 18253676800 -// CHECK-NEXT: [[TMP75:%.*]] = and i1 true, [[TMP74]] -// CHECK-NEXT: br i1 [[TMP75]], label [[RESOLVER_RETURN35:%.*]], label [[RESOLVER_ELSE36:%.*]] -// CHECK: resolver_return35: -// CHECK-NEXT: ret ptr @fmv._Mf32mm -// CHECK: resolver_else36: -// CHECK-NEXT: [[TMP76:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP77:%.*]] = and i64 [[TMP76]], 1073807616 -// CHECK-NEXT: [[TMP78:%.*]] = icmp eq i64 [[TMP77]], 1073807616 -// CHECK-NEXT: [[TMP79:%.*]] = and i1 true, [[TMP78]] -// CHECK-NEXT: br i1 [[TMP79]], label [[RESOLVER_RETURN37:%.*]], label [[RESOLVER_ELSE38:%.*]] -// CHECK: resolver_return37: -// CHECK-NEXT: ret ptr @fmv._Msve -// CHECK: resolver_else38: -// CHECK-NEXT: [[TMP80:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP81:%.*]] = and i64 [[TMP80]], 134218496 -// CHECK-NEXT: [[TMP82:%.*]] = icmp eq i64 [[TMP81]], 134218496 -// CHECK-NEXT: [[TMP83:%.*]] = and i1 true, [[TMP82]] -// CHECK-NEXT: br i1 [[TMP83]], label [[RESOLVER_RETURN39:%.*]], label [[RESOLVER_ELSE40:%.*]] -// CHECK: resolver_return39: -// CHECK-NEXT: ret ptr @fmv._Mbf16 -// CHECK: resolver_else40: -// CHECK-NEXT: [[TMP84:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP85:%.*]] = and i64 [[TMP84]], 67109632 -// CHECK-NEXT: [[TMP86:%.*]] = icmp eq i64 [[TMP85]], 67109632 -// CHECK-NEXT: [[TMP87:%.*]] = and i1 true, [[TMP86]] -// CHECK-NEXT: br i1 [[TMP87]], label [[RESOLVER_RETURN41:%.*]], label [[RESOLVER_ELSE42:%.*]] -// CHECK: resolver_return41: -// CHECK-NEXT: ret ptr @fmv._Mi8mm -// CHECK: resolver_else42: -// CHECK-NEXT: [[TMP88:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP89:%.*]] = and i64 [[TMP88]], 16777472 -// CHECK-NEXT: [[TMP90:%.*]] = icmp eq i64 [[TMP89]], 16777472 -// CHECK-NEXT: [[TMP91:%.*]] = and i1 true, [[TMP90]] -// CHECK-NEXT: br i1 [[TMP91]], label [[RESOLVER_RETURN43:%.*]], label [[RESOLVER_ELSE44:%.*]] -// CHECK: resolver_return43: -// CHECK-NEXT: ret ptr @fmv._Mfrintts -// CHECK: resolver_else44: -// CHECK-NEXT: [[TMP92:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP93:%.*]] = and i64 [[TMP92]], 288230376164294656 -// CHECK-NEXT: [[TMP94:%.*]] = icmp eq i64 [[TMP93]], 288230376164294656 -// CHECK-NEXT: [[TMP95:%.*]] = and i1 true, [[TMP94]] -// CHECK-NEXT: br i1 [[TMP95]], label [[RESOLVER_RETURN45:%.*]], label [[RESOLVER_ELSE46:%.*]] -// CHECK: resolver_return45: -// CHECK-NEXT: ret ptr @fmv._Mrcpc3 -// CHECK: resolver_else46: -// CHECK-NEXT: [[TMP96:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP97:%.*]] = and i64 [[TMP96]], 12582912 -// CHECK-NEXT: [[TMP98:%.*]] = icmp eq i64 [[TMP97]], 12582912 -// CHECK-NEXT: [[TMP99:%.*]] = and i1 true, [[TMP98]] -// CHECK-NEXT: br i1 [[TMP99]], label [[RESOLVER_RETURN47:%.*]], label [[RESOLVER_ELSE48:%.*]] -// CHECK: resolver_return47: -// CHECK-NEXT: ret ptr @fmv._Mrcpc2 -// CHECK: resolver_else48: -// CHECK-NEXT: [[TMP100:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP101:%.*]] = and i64 [[TMP100]], 4194304 -// CHECK-NEXT: [[TMP102:%.*]] = icmp eq i64 [[TMP101]], 4194304 -// CHECK-NEXT: [[TMP103:%.*]] = and i1 true, [[TMP102]] -// CHECK-NEXT: br i1 [[TMP103]], label [[RESOLVER_RETURN49:%.*]], label [[RESOLVER_ELSE50:%.*]] -// CHECK: resolver_return49: -// CHECK-NEXT: ret ptr @fmv._Mrcpc -// CHECK: resolver_else50: -// CHECK-NEXT: [[TMP104:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP105:%.*]] = and i64 [[TMP104]], 2097920 -// CHECK-NEXT: [[TMP106:%.*]] = icmp eq i64 [[TMP105]], 2097920 -// CHECK-NEXT: [[TMP107:%.*]] = and i1 true, [[TMP106]] -// CHECK-NEXT: br i1 [[TMP107]], label [[RESOLVER_RETURN51:%.*]], label [[RESOLVER_ELSE52:%.*]] -// CHECK: resolver_return51: -// CHECK-NEXT: ret ptr @fmv._Mfcma -// CHECK: resolver_else52: -// CHECK-NEXT: [[TMP108:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP109:%.*]] = and i64 [[TMP108]], 1048832 -// CHECK-NEXT: [[TMP110:%.*]] = icmp eq i64 [[TMP109]], 1048832 -// CHECK-NEXT: [[TMP111:%.*]] = and i1 true, [[TMP110]] -// CHECK-NEXT: br i1 [[TMP111]], label [[RESOLVER_RETURN53:%.*]], label [[RESOLVER_ELSE54:%.*]] -// CHECK: resolver_return53: -// CHECK-NEXT: ret ptr @fmv._Mjscvt -// CHECK: resolver_else54: -// CHECK-NEXT: [[TMP112:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP113:%.*]] = and i64 [[TMP112]], 786432 -// CHECK-NEXT: [[TMP114:%.*]] = icmp eq i64 [[TMP113]], 786432 -// CHECK-NEXT: [[TMP115:%.*]] = and i1 true, [[TMP114]] -// CHECK-NEXT: br i1 [[TMP115]], label [[RESOLVER_RETURN55:%.*]], label [[RESOLVER_ELSE56:%.*]] -// CHECK: resolver_return55: -// CHECK-NEXT: ret ptr @fmv._Mdpb2 -// CHECK: resolver_else56: -// CHECK-NEXT: [[TMP116:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP117:%.*]] = and i64 [[TMP116]], 262144 -// CHECK-NEXT: [[TMP118:%.*]] = icmp eq i64 [[TMP117]], 262144 -// CHECK-NEXT: [[TMP119:%.*]] = and i1 true, [[TMP118]] -// CHECK-NEXT: br i1 [[TMP119]], label [[RESOLVER_RETURN57:%.*]], label [[RESOLVER_ELSE58:%.*]] -// CHECK: resolver_return57: -// CHECK-NEXT: ret ptr @fmv._Mdpb -// CHECK: resolver_else58: -// CHECK-NEXT: [[TMP120:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP121:%.*]] = and i64 [[TMP120]], 131072 -// CHECK-NEXT: [[TMP122:%.*]] = icmp eq i64 [[TMP121]], 131072 -// CHECK-NEXT: [[TMP123:%.*]] = and i1 true, [[TMP122]] -// CHECK-NEXT: br i1 [[TMP123]], label [[RESOLVER_RETURN59:%.*]], label [[RESOLVER_ELSE60:%.*]] -// CHECK: resolver_return59: -// CHECK-NEXT: ret ptr @fmv._Mdit -// CHECK: resolver_else60: -// CHECK-NEXT: [[TMP124:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP125:%.*]] = and i64 [[TMP124]], 66312 -// CHECK-NEXT: [[TMP126:%.*]] = icmp eq i64 [[TMP125]], 66312 -// CHECK-NEXT: [[TMP127:%.*]] = and i1 true, [[TMP126]] -// CHECK-NEXT: br i1 [[TMP127]], label [[RESOLVER_RETURN61:%.*]], label [[RESOLVER_ELSE62:%.*]] -// CHECK: resolver_return61: -// CHECK-NEXT: ret ptr @fmv._Mfp16fml -// CHECK: resolver_else62: -// CHECK-NEXT: [[TMP128:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP129:%.*]] = and i64 [[TMP128]], 65792 -// CHECK-NEXT: [[TMP130:%.*]] = icmp eq i64 [[TMP129]], 65792 -// CHECK-NEXT: [[TMP131:%.*]] = and i1 true, [[TMP130]] -// CHECK-NEXT: br i1 [[TMP131]], label [[RESOLVER_RETURN63:%.*]], label [[RESOLVER_ELSE64:%.*]] -// CHECK: resolver_return63: -// CHECK-NEXT: ret ptr @fmv._Mfp16 -// CHECK: resolver_else64: -// CHECK-NEXT: [[TMP132:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP133:%.*]] = and i64 [[TMP132]], 33536 -// CHECK-NEXT: [[TMP134:%.*]] = icmp eq i64 [[TMP133]], 33536 -// CHECK-NEXT: [[TMP135:%.*]] = and i1 true, [[TMP134]] -// CHECK-NEXT: br i1 [[TMP135]], label [[RESOLVER_RETURN65:%.*]], label [[RESOLVER_ELSE66:%.*]] -// CHECK: resolver_return65: -// CHECK-NEXT: ret ptr @fmv._Maes -// CHECK: resolver_else66: -// CHECK-NEXT: [[TMP136:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP137:%.*]] = and i64 [[TMP136]], 13056 -// CHECK-NEXT: [[TMP138:%.*]] = icmp eq i64 [[TMP137]], 13056 -// CHECK-NEXT: [[TMP139:%.*]] = and i1 true, [[TMP138]] -// CHECK-NEXT: br i1 [[TMP139]], label [[RESOLVER_RETURN67:%.*]], label [[RESOLVER_ELSE68:%.*]] -// CHECK: resolver_return67: -// CHECK-NEXT: ret ptr @fmv._Msha3 -// CHECK: resolver_else68: -// CHECK-NEXT: [[TMP140:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP141:%.*]] = and i64 [[TMP140]], 4864 -// CHECK-NEXT: [[TMP142:%.*]] = icmp eq i64 [[TMP141]], 4864 -// CHECK-NEXT: [[TMP143:%.*]] = and i1 true, [[TMP142]] -// CHECK-NEXT: br i1 [[TMP143]], label [[RESOLVER_RETURN69:%.*]], label [[RESOLVER_ELSE70:%.*]] -// CHECK: resolver_return69: -// CHECK-NEXT: ret ptr @fmv._Msha2 -// CHECK: resolver_else70: -// CHECK-NEXT: [[TMP144:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP145:%.*]] = and i64 [[TMP144]], 1024 -// CHECK-NEXT: [[TMP146:%.*]] = icmp eq i64 [[TMP145]], 1024 -// CHECK-NEXT: [[TMP147:%.*]] = and i1 true, [[TMP146]] -// CHECK-NEXT: br i1 [[TMP147]], label [[RESOLVER_RETURN71:%.*]], label [[RESOLVER_ELSE72:%.*]] -// CHECK: resolver_return71: -// CHECK-NEXT: ret ptr @fmv._Mcrc -// CHECK: resolver_else72: -// CHECK-NEXT: [[TMP148:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP149:%.*]] = and i64 [[TMP148]], 832 -// CHECK-NEXT: [[TMP150:%.*]] = icmp eq i64 [[TMP149]], 832 -// CHECK-NEXT: [[TMP151:%.*]] = and i1 true, [[TMP150]] -// CHECK-NEXT: br i1 [[TMP151]], label [[RESOLVER_RETURN73:%.*]], label [[RESOLVER_ELSE74:%.*]] -// CHECK: resolver_return73: -// CHECK-NEXT: ret ptr @fmv._Mrdm -// CHECK: resolver_else74: -// CHECK-NEXT: [[TMP152:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP153:%.*]] = and i64 [[TMP152]], 800 -// CHECK-NEXT: [[TMP154:%.*]] = icmp eq i64 [[TMP153]], 800 -// CHECK-NEXT: [[TMP155:%.*]] = and i1 true, [[TMP154]] -// CHECK-NEXT: br i1 [[TMP155]], label [[RESOLVER_RETURN75:%.*]], label [[RESOLVER_ELSE76:%.*]] -// CHECK: resolver_return75: -// CHECK-NEXT: ret ptr @fmv._Msm4 -// CHECK: resolver_else76: -// CHECK-NEXT: [[TMP156:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP157:%.*]] = and i64 [[TMP156]], 784 -// CHECK-NEXT: [[TMP158:%.*]] = icmp eq i64 [[TMP157]], 784 -// CHECK-NEXT: [[TMP159:%.*]] = and i1 true, [[TMP158]] -// CHECK-NEXT: br i1 [[TMP159]], label [[RESOLVER_RETURN77:%.*]], label [[RESOLVER_ELSE78:%.*]] -// CHECK: resolver_return77: -// CHECK-NEXT: ret ptr @fmv._Mdotprod -// CHECK: resolver_else78: -// CHECK-NEXT: [[TMP160:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP161:%.*]] = and i64 [[TMP160]], 768 -// CHECK-NEXT: [[TMP162:%.*]] = icmp eq i64 [[TMP161]], 768 -// CHECK-NEXT: [[TMP163:%.*]] = and i1 true, [[TMP162]] -// CHECK-NEXT: br i1 [[TMP163]], label [[RESOLVER_RETURN79:%.*]], label [[RESOLVER_ELSE80:%.*]] -// CHECK: resolver_return79: -// CHECK-NEXT: ret ptr @fmv._Msimd -// CHECK: resolver_else80: -// CHECK-NEXT: [[TMP164:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP165:%.*]] = and i64 [[TMP164]], 256 -// CHECK-NEXT: [[TMP166:%.*]] = icmp eq i64 [[TMP165]], 256 -// CHECK-NEXT: [[TMP167:%.*]] = and i1 true, [[TMP166]] -// CHECK-NEXT: br i1 [[TMP167]], label [[RESOLVER_RETURN81:%.*]], label [[RESOLVER_ELSE82:%.*]] -// CHECK: resolver_return81: -// CHECK-NEXT: ret ptr @fmv._Mfp -// CHECK: resolver_else82: -// CHECK-NEXT: [[TMP168:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP169:%.*]] = and i64 [[TMP168]], 128 -// CHECK-NEXT: [[TMP170:%.*]] = icmp eq i64 [[TMP169]], 128 -// CHECK-NEXT: [[TMP171:%.*]] = and i1 true, [[TMP170]] -// CHECK-NEXT: br i1 [[TMP171]], label [[RESOLVER_RETURN83:%.*]], label [[RESOLVER_ELSE84:%.*]] -// CHECK: resolver_return83: -// CHECK-NEXT: ret ptr @fmv._Mlse -// CHECK: resolver_else84: -// CHECK-NEXT: [[TMP172:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP173:%.*]] = and i64 [[TMP172]], 6 -// CHECK-NEXT: [[TMP174:%.*]] = icmp eq i64 [[TMP173]], 6 -// CHECK-NEXT: [[TMP175:%.*]] = and i1 true, [[TMP174]] -// CHECK-NEXT: br i1 [[TMP175]], label [[RESOLVER_RETURN85:%.*]], label [[RESOLVER_ELSE86:%.*]] -// CHECK: resolver_return85: -// CHECK-NEXT: ret ptr @fmv._Mflagm2 -// CHECK: resolver_else86: -// CHECK-NEXT: [[TMP176:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP177:%.*]] = and i64 [[TMP176]], 2 -// CHECK-NEXT: [[TMP178:%.*]] = icmp eq i64 [[TMP177]], 2 -// CHECK-NEXT: [[TMP179:%.*]] = and i1 true, [[TMP178]] -// CHECK-NEXT: br i1 [[TMP179]], label [[RESOLVER_RETURN87:%.*]], label [[RESOLVER_ELSE88:%.*]] -// CHECK: resolver_return87: -// CHECK-NEXT: ret ptr @fmv._Mflagm -// CHECK: resolver_else88: -// CHECK-NEXT: [[TMP180:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP181:%.*]] = and i64 [[TMP180]], 1 -// CHECK-NEXT: [[TMP182:%.*]] = icmp eq i64 [[TMP181]], 1 -// CHECK-NEXT: [[TMP183:%.*]] = and i1 true, [[TMP182]] -// CHECK-NEXT: br i1 [[TMP183]], label [[RESOLVER_RETURN89:%.*]], label [[RESOLVER_ELSE90:%.*]] -// CHECK: resolver_return89: -// CHECK-NEXT: ret ptr @fmv._Mrng -// CHECK: resolver_else90: -// CHECK-NEXT: ret ptr @fmv.default -// -// // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@fmv._Mbti // CHECK-SAME: () #[[ATTR2:[0-9]+]] { @@ -544,14 +170,14 @@ int caller() { // CHECK-NEXT: ret i32 0 // // -// CHECK: Function Attrs: noinline nounwind optnone +// CHECK: Function Attrs: noinline nounwind optnone vscale_range(1,16) // CHECK-LABEL: define {{[^@]+}}@fmv._Mf32mm // CHECK-SAME: () #[[ATTR9:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 0 // // -// CHECK: Function Attrs: noinline nounwind optnone +// CHECK: Function Attrs: noinline nounwind optnone vscale_range(1,16) // CHECK-LABEL: define {{[^@]+}}@fmv._Mf64mm // CHECK-SAME: () #[[ATTR10:[0-9]+]] { // CHECK-NEXT: entry: @@ -747,42 +373,42 @@ int caller() { // CHECK-NEXT: ret i32 0 // // -// CHECK: Function Attrs: noinline nounwind optnone +// CHECK: Function Attrs: noinline nounwind optnone vscale_range(1,16) // CHECK-LABEL: define {{[^@]+}}@fmv._Msve // CHECK-SAME: () #[[ATTR38:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 0 // // -// CHECK: Function Attrs: noinline nounwind optnone +// CHECK: Function Attrs: noinline nounwind optnone vscale_range(1,16) // CHECK-LABEL: define {{[^@]+}}@fmv._Msve2 // CHECK-SAME: () #[[ATTR39:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 0 // // -// CHECK: Function Attrs: noinline nounwind optnone +// CHECK: Function Attrs: noinline nounwind optnone vscale_range(1,16) // CHECK-LABEL: define {{[^@]+}}@fmv._Msve2-aes // CHECK-SAME: () #[[ATTR40:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 0 // // -// CHECK: Function Attrs: noinline nounwind optnone +// CHECK: Function Attrs: noinline nounwind optnone vscale_range(1,16) // CHECK-LABEL: define {{[^@]+}}@fmv._Msve2-bitperm // CHECK-SAME: () #[[ATTR41:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 0 // // -// CHECK: Function Attrs: noinline nounwind optnone +// CHECK: Function Attrs: noinline nounwind optnone vscale_range(1,16) // CHECK-LABEL: define {{[^@]+}}@fmv._Msve2-sha3 // CHECK-SAME: () #[[ATTR42:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 0 // // -// CHECK: Function Attrs: noinline nounwind optnone +// CHECK: Function Attrs: noinline nounwind optnone vscale_range(1,16) // CHECK-LABEL: define {{[^@]+}}@fmv._Msve2-sm4 // CHECK-SAME: () #[[ATTR43:[0-9]+]] { // CHECK-NEXT: entry: @@ -797,18 +423,392 @@ int caller() { // // // CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@caller +// CHECK-LABEL: define {{[^@]+}}@fmv.default // CHECK-SAME: () #[[ATTR45:[0-9]+]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[CALL:%.*]] = call i32 @fmv() -// CHECK-NEXT: ret i32 [[CALL]] +// CHECK-NEXT: ret i32 0 // // // CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv.default +// CHECK-LABEL: define {{[^@]+}}@caller // CHECK-SAME: () #[[ATTR46:[0-9]+]] { // CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 0 +// CHECK-NEXT: [[CALL:%.*]] = call i32 @fmv() +// CHECK-NEXT: ret i32 [[CALL]] +// +// +// CHECK-LABEL: define {{[^@]+}}@fmv.resolver() comdat { +// CHECK-NEXT: resolver_entry: +// CHECK-NEXT: call void @__init_cpu_features_resolver() +// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 2304 +// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 2304 +// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] +// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] +// CHECK: resolver_return: +// CHECK-NEXT: ret ptr @fmv._McsscMfp +// CHECK: resolver_else: +// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 2048 +// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 2048 +// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] +// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] +// CHECK: resolver_return1: +// CHECK-NEXT: ret ptr @fmv._Mcssc +// CHECK: resolver_else2: +// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 576460752303423488 +// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 576460752303423488 +// CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]] +// CHECK-NEXT: br i1 [[TMP11]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]] +// CHECK: resolver_return3: +// CHECK-NEXT: ret ptr @fmv._Mmops +// CHECK: resolver_else4: +// CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP13:%.*]] = and i64 [[TMP12]], 144119586256651008 +// CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[TMP13]], 144119586256651008 +// CHECK-NEXT: [[TMP15:%.*]] = and i1 true, [[TMP14]] +// CHECK-NEXT: br i1 [[TMP15]], label [[RESOLVER_RETURN5:%.*]], label [[RESOLVER_ELSE6:%.*]] +// CHECK: resolver_return5: +// CHECK-NEXT: ret ptr @fmv._Msme2 +// CHECK: resolver_else6: +// CHECK-NEXT: [[TMP16:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP17:%.*]] = and i64 [[TMP16]], 72061992218723072 +// CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[TMP17]], 72061992218723072 +// CHECK-NEXT: [[TMP19:%.*]] = and i1 true, [[TMP18]] +// CHECK-NEXT: br i1 [[TMP19]], label [[RESOLVER_RETURN7:%.*]], label [[RESOLVER_ELSE8:%.*]] +// CHECK: resolver_return7: +// CHECK-NEXT: ret ptr @fmv._Msme-i16i64 +// CHECK: resolver_else8: +// CHECK-NEXT: [[TMP20:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP21:%.*]] = and i64 [[TMP20]], 36033195199759104 +// CHECK-NEXT: [[TMP22:%.*]] = icmp eq i64 [[TMP21]], 36033195199759104 +// CHECK-NEXT: [[TMP23:%.*]] = and i1 true, [[TMP22]] +// CHECK-NEXT: br i1 [[TMP23]], label [[RESOLVER_RETURN9:%.*]], label [[RESOLVER_ELSE10:%.*]] +// CHECK: resolver_return9: +// CHECK-NEXT: ret ptr @fmv._Msme-f64f64 +// CHECK: resolver_else10: +// CHECK-NEXT: [[TMP24:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP25:%.*]] = and i64 [[TMP24]], 18014398509481984 +// CHECK-NEXT: [[TMP26:%.*]] = icmp eq i64 [[TMP25]], 18014398509481984 +// CHECK-NEXT: [[TMP27:%.*]] = and i1 true, [[TMP26]] +// CHECK-NEXT: br i1 [[TMP27]], label [[RESOLVER_RETURN11:%.*]], label [[RESOLVER_ELSE12:%.*]] +// CHECK: resolver_return11: +// CHECK-NEXT: ret ptr @fmv._Mwfxt +// CHECK: resolver_else12: +// CHECK-NEXT: [[TMP28:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP29:%.*]] = and i64 [[TMP28]], 1125899906842624 +// CHECK-NEXT: [[TMP30:%.*]] = icmp eq i64 [[TMP29]], 1125899906842624 +// CHECK-NEXT: [[TMP31:%.*]] = and i1 true, [[TMP30]] +// CHECK-NEXT: br i1 [[TMP31]], label [[RESOLVER_RETURN13:%.*]], label [[RESOLVER_ELSE14:%.*]] +// CHECK: resolver_return13: +// CHECK-NEXT: ret ptr @fmv._Mbti +// CHECK: resolver_else14: +// CHECK-NEXT: [[TMP32:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP33:%.*]] = and i64 [[TMP32]], 562949953421312 +// CHECK-NEXT: [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 562949953421312 +// CHECK-NEXT: [[TMP35:%.*]] = and i1 true, [[TMP34]] +// CHECK-NEXT: br i1 [[TMP35]], label [[RESOLVER_RETURN15:%.*]], label [[RESOLVER_ELSE16:%.*]] +// CHECK: resolver_return15: +// CHECK-NEXT: ret ptr @fmv._Mssbs +// CHECK: resolver_else16: +// CHECK-NEXT: [[TMP36:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP37:%.*]] = and i64 [[TMP36]], 70368744177664 +// CHECK-NEXT: [[TMP38:%.*]] = icmp eq i64 [[TMP37]], 70368744177664 +// CHECK-NEXT: [[TMP39:%.*]] = and i1 true, [[TMP38]] +// CHECK-NEXT: br i1 [[TMP39]], label [[RESOLVER_RETURN17:%.*]], label [[RESOLVER_ELSE18:%.*]] +// CHECK: resolver_return17: +// CHECK-NEXT: ret ptr @fmv._Msb +// CHECK: resolver_else18: +// CHECK-NEXT: [[TMP40:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP41:%.*]] = and i64 [[TMP40]], 17592186044416 +// CHECK-NEXT: [[TMP42:%.*]] = icmp eq i64 [[TMP41]], 17592186044416 +// CHECK-NEXT: [[TMP43:%.*]] = and i1 true, [[TMP42]] +// CHECK-NEXT: br i1 [[TMP43]], label [[RESOLVER_RETURN19:%.*]], label [[RESOLVER_ELSE20:%.*]] +// CHECK: resolver_return19: +// CHECK-NEXT: ret ptr @fmv._Mmemtag +// CHECK: resolver_else20: +// CHECK-NEXT: [[TMP44:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP45:%.*]] = and i64 [[TMP44]], 4398180795136 +// CHECK-NEXT: [[TMP46:%.*]] = icmp eq i64 [[TMP45]], 4398180795136 +// CHECK-NEXT: [[TMP47:%.*]] = and i1 true, [[TMP46]] +// CHECK-NEXT: br i1 [[TMP47]], label [[RESOLVER_RETURN21:%.*]], label [[RESOLVER_ELSE22:%.*]] +// CHECK: resolver_return21: +// CHECK-NEXT: ret ptr @fmv._Msme +// CHECK: resolver_else22: +// CHECK-NEXT: [[TMP48:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP49:%.*]] = and i64 [[TMP48]], 2268816540448 +// CHECK-NEXT: [[TMP50:%.*]] = icmp eq i64 [[TMP49]], 2268816540448 +// CHECK-NEXT: [[TMP51:%.*]] = and i1 true, [[TMP50]] +// CHECK-NEXT: br i1 [[TMP51]], label [[RESOLVER_RETURN23:%.*]], label [[RESOLVER_ELSE24:%.*]] +// CHECK: resolver_return23: +// CHECK-NEXT: ret ptr @fmv._Msve2-sm4 +// CHECK: resolver_else24: +// CHECK-NEXT: [[TMP52:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP53:%.*]] = and i64 [[TMP52]], 1169304924928 +// CHECK-NEXT: [[TMP54:%.*]] = icmp eq i64 [[TMP53]], 1169304924928 +// CHECK-NEXT: [[TMP55:%.*]] = and i1 true, [[TMP54]] +// CHECK-NEXT: br i1 [[TMP55]], label [[RESOLVER_RETURN25:%.*]], label [[RESOLVER_ELSE26:%.*]] +// CHECK: resolver_return25: +// CHECK-NEXT: ret ptr @fmv._Msve2-sha3 +// CHECK: resolver_else26: +// CHECK-NEXT: [[TMP56:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP57:%.*]] = and i64 [[TMP56]], 619549098240 +// CHECK-NEXT: [[TMP58:%.*]] = icmp eq i64 [[TMP57]], 619549098240 +// CHECK-NEXT: [[TMP59:%.*]] = and i1 true, [[TMP58]] +// CHECK-NEXT: br i1 [[TMP59]], label [[RESOLVER_RETURN27:%.*]], label [[RESOLVER_ELSE28:%.*]] +// CHECK: resolver_return27: +// CHECK-NEXT: ret ptr @fmv._Msve2-bitperm +// CHECK: resolver_else28: +// CHECK-NEXT: [[TMP60:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP61:%.*]] = and i64 [[TMP60]], 344671224576 +// CHECK-NEXT: [[TMP62:%.*]] = icmp eq i64 [[TMP61]], 344671224576 +// CHECK-NEXT: [[TMP63:%.*]] = and i1 true, [[TMP62]] +// CHECK-NEXT: br i1 [[TMP63]], label [[RESOLVER_RETURN29:%.*]], label [[RESOLVER_ELSE30:%.*]] +// CHECK: resolver_return29: +// CHECK-NEXT: ret ptr @fmv._Msve2-aes +// CHECK: resolver_else30: +// CHECK-NEXT: [[TMP64:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP65:%.*]] = and i64 [[TMP64]], 69793284352 +// CHECK-NEXT: [[TMP66:%.*]] = icmp eq i64 [[TMP65]], 69793284352 +// CHECK-NEXT: [[TMP67:%.*]] = and i1 true, [[TMP66]] +// CHECK-NEXT: br i1 [[TMP67]], label [[RESOLVER_RETURN31:%.*]], label [[RESOLVER_ELSE32:%.*]] +// CHECK: resolver_return31: +// CHECK-NEXT: ret ptr @fmv._Msve2 +// CHECK: resolver_else32: +// CHECK-NEXT: [[TMP68:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP69:%.*]] = and i64 [[TMP68]], 35433545984 +// CHECK-NEXT: [[TMP70:%.*]] = icmp eq i64 [[TMP69]], 35433545984 +// CHECK-NEXT: [[TMP71:%.*]] = and i1 true, [[TMP70]] +// CHECK-NEXT: br i1 [[TMP71]], label [[RESOLVER_RETURN33:%.*]], label [[RESOLVER_ELSE34:%.*]] +// CHECK: resolver_return33: +// CHECK-NEXT: ret ptr @fmv._Mf64mm +// CHECK: resolver_else34: +// CHECK-NEXT: [[TMP72:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP73:%.*]] = and i64 [[TMP72]], 18253676800 +// CHECK-NEXT: [[TMP74:%.*]] = icmp eq i64 [[TMP73]], 18253676800 +// CHECK-NEXT: [[TMP75:%.*]] = and i1 true, [[TMP74]] +// CHECK-NEXT: br i1 [[TMP75]], label [[RESOLVER_RETURN35:%.*]], label [[RESOLVER_ELSE36:%.*]] +// CHECK: resolver_return35: +// CHECK-NEXT: ret ptr @fmv._Mf32mm +// CHECK: resolver_else36: +// CHECK-NEXT: [[TMP76:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP77:%.*]] = and i64 [[TMP76]], 1073807616 +// CHECK-NEXT: [[TMP78:%.*]] = icmp eq i64 [[TMP77]], 1073807616 +// CHECK-NEXT: [[TMP79:%.*]] = and i1 true, [[TMP78]] +// CHECK-NEXT: br i1 [[TMP79]], label [[RESOLVER_RETURN37:%.*]], label [[RESOLVER_ELSE38:%.*]] +// CHECK: resolver_return37: +// CHECK-NEXT: ret ptr @fmv._Msve +// CHECK: resolver_else38: +// CHECK-NEXT: [[TMP80:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP81:%.*]] = and i64 [[TMP80]], 134218496 +// CHECK-NEXT: [[TMP82:%.*]] = icmp eq i64 [[TMP81]], 134218496 +// CHECK-NEXT: [[TMP83:%.*]] = and i1 true, [[TMP82]] +// CHECK-NEXT: br i1 [[TMP83]], label [[RESOLVER_RETURN39:%.*]], label [[RESOLVER_ELSE40:%.*]] +// CHECK: resolver_return39: +// CHECK-NEXT: ret ptr @fmv._Mbf16 +// CHECK: resolver_else40: +// CHECK-NEXT: [[TMP84:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP85:%.*]] = and i64 [[TMP84]], 67109632 +// CHECK-NEXT: [[TMP86:%.*]] = icmp eq i64 [[TMP85]], 67109632 +// CHECK-NEXT: [[TMP87:%.*]] = and i1 true, [[TMP86]] +// CHECK-NEXT: br i1 [[TMP87]], label [[RESOLVER_RETURN41:%.*]], label [[RESOLVER_ELSE42:%.*]] +// CHECK: resolver_return41: +// CHECK-NEXT: ret ptr @fmv._Mi8mm +// CHECK: resolver_else42: +// CHECK-NEXT: [[TMP88:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP89:%.*]] = and i64 [[TMP88]], 16777472 +// CHECK-NEXT: [[TMP90:%.*]] = icmp eq i64 [[TMP89]], 16777472 +// CHECK-NEXT: [[TMP91:%.*]] = and i1 true, [[TMP90]] +// CHECK-NEXT: br i1 [[TMP91]], label [[RESOLVER_RETURN43:%.*]], label [[RESOLVER_ELSE44:%.*]] +// CHECK: resolver_return43: +// CHECK-NEXT: ret ptr @fmv._Mfrintts +// CHECK: resolver_else44: +// CHECK-NEXT: [[TMP92:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP93:%.*]] = and i64 [[TMP92]], 288230376164294656 +// CHECK-NEXT: [[TMP94:%.*]] = icmp eq i64 [[TMP93]], 288230376164294656 +// CHECK-NEXT: [[TMP95:%.*]] = and i1 true, [[TMP94]] +// CHECK-NEXT: br i1 [[TMP95]], label [[RESOLVER_RETURN45:%.*]], label [[RESOLVER_ELSE46:%.*]] +// CHECK: resolver_return45: +// CHECK-NEXT: ret ptr @fmv._Mrcpc3 +// CHECK: resolver_else46: +// CHECK-NEXT: [[TMP96:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP97:%.*]] = and i64 [[TMP96]], 12582912 +// CHECK-NEXT: [[TMP98:%.*]] = icmp eq i64 [[TMP97]], 12582912 +// CHECK-NEXT: [[TMP99:%.*]] = and i1 true, [[TMP98]] +// CHECK-NEXT: br i1 [[TMP99]], label [[RESOLVER_RETURN47:%.*]], label [[RESOLVER_ELSE48:%.*]] +// CHECK: resolver_return47: +// CHECK-NEXT: ret ptr @fmv._Mrcpc2 +// CHECK: resolver_else48: +// CHECK-NEXT: [[TMP100:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP101:%.*]] = and i64 [[TMP100]], 4194304 +// CHECK-NEXT: [[TMP102:%.*]] = icmp eq i64 [[TMP101]], 4194304 +// CHECK-NEXT: [[TMP103:%.*]] = and i1 true, [[TMP102]] +// CHECK-NEXT: br i1 [[TMP103]], label [[RESOLVER_RETURN49:%.*]], label [[RESOLVER_ELSE50:%.*]] +// CHECK: resolver_return49: +// CHECK-NEXT: ret ptr @fmv._Mrcpc +// CHECK: resolver_else50: +// CHECK-NEXT: [[TMP104:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP105:%.*]] = and i64 [[TMP104]], 2097920 +// CHECK-NEXT: [[TMP106:%.*]] = icmp eq i64 [[TMP105]], 2097920 +// CHECK-NEXT: [[TMP107:%.*]] = and i1 true, [[TMP106]] +// CHECK-NEXT: br i1 [[TMP107]], label [[RESOLVER_RETURN51:%.*]], label [[RESOLVER_ELSE52:%.*]] +// CHECK: resolver_return51: +// CHECK-NEXT: ret ptr @fmv._Mfcma +// CHECK: resolver_else52: +// CHECK-NEXT: [[TMP108:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP109:%.*]] = and i64 [[TMP108]], 1048832 +// CHECK-NEXT: [[TMP110:%.*]] = icmp eq i64 [[TMP109]], 1048832 +// CHECK-NEXT: [[TMP111:%.*]] = and i1 true, [[TMP110]] +// CHECK-NEXT: br i1 [[TMP111]], label [[RESOLVER_RETURN53:%.*]], label [[RESOLVER_ELSE54:%.*]] +// CHECK: resolver_return53: +// CHECK-NEXT: ret ptr @fmv._Mjscvt +// CHECK: resolver_else54: +// CHECK-NEXT: [[TMP112:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP113:%.*]] = and i64 [[TMP112]], 786432 +// CHECK-NEXT: [[TMP114:%.*]] = icmp eq i64 [[TMP113]], 786432 +// CHECK-NEXT: [[TMP115:%.*]] = and i1 true, [[TMP114]] +// CHECK-NEXT: br i1 [[TMP115]], label [[RESOLVER_RETURN55:%.*]], label [[RESOLVER_ELSE56:%.*]] +// CHECK: resolver_return55: +// CHECK-NEXT: ret ptr @fmv._Mdpb2 +// CHECK: resolver_else56: +// CHECK-NEXT: [[TMP116:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP117:%.*]] = and i64 [[TMP116]], 262144 +// CHECK-NEXT: [[TMP118:%.*]] = icmp eq i64 [[TMP117]], 262144 +// CHECK-NEXT: [[TMP119:%.*]] = and i1 true, [[TMP118]] +// CHECK-NEXT: br i1 [[TMP119]], label [[RESOLVER_RETURN57:%.*]], label [[RESOLVER_ELSE58:%.*]] +// CHECK: resolver_return57: +// CHECK-NEXT: ret ptr @fmv._Mdpb +// CHECK: resolver_else58: +// CHECK-NEXT: [[TMP120:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP121:%.*]] = and i64 [[TMP120]], 131072 +// CHECK-NEXT: [[TMP122:%.*]] = icmp eq i64 [[TMP121]], 131072 +// CHECK-NEXT: [[TMP123:%.*]] = and i1 true, [[TMP122]] +// CHECK-NEXT: br i1 [[TMP123]], label [[RESOLVER_RETURN59:%.*]], label [[RESOLVER_ELSE60:%.*]] +// CHECK: resolver_return59: +// CHECK-NEXT: ret ptr @fmv._Mdit +// CHECK: resolver_else60: +// CHECK-NEXT: [[TMP124:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP125:%.*]] = and i64 [[TMP124]], 66312 +// CHECK-NEXT: [[TMP126:%.*]] = icmp eq i64 [[TMP125]], 66312 +// CHECK-NEXT: [[TMP127:%.*]] = and i1 true, [[TMP126]] +// CHECK-NEXT: br i1 [[TMP127]], label [[RESOLVER_RETURN61:%.*]], label [[RESOLVER_ELSE62:%.*]] +// CHECK: resolver_return61: +// CHECK-NEXT: ret ptr @fmv._Mfp16fml +// CHECK: resolver_else62: +// CHECK-NEXT: [[TMP128:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP129:%.*]] = and i64 [[TMP128]], 65792 +// CHECK-NEXT: [[TMP130:%.*]] = icmp eq i64 [[TMP129]], 65792 +// CHECK-NEXT: [[TMP131:%.*]] = and i1 true, [[TMP130]] +// CHECK-NEXT: br i1 [[TMP131]], label [[RESOLVER_RETURN63:%.*]], label [[RESOLVER_ELSE64:%.*]] +// CHECK: resolver_return63: +// CHECK-NEXT: ret ptr @fmv._Mfp16 +// CHECK: resolver_else64: +// CHECK-NEXT: [[TMP132:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP133:%.*]] = and i64 [[TMP132]], 33536 +// CHECK-NEXT: [[TMP134:%.*]] = icmp eq i64 [[TMP133]], 33536 +// CHECK-NEXT: [[TMP135:%.*]] = and i1 true, [[TMP134]] +// CHECK-NEXT: br i1 [[TMP135]], label [[RESOLVER_RETURN65:%.*]], label [[RESOLVER_ELSE66:%.*]] +// CHECK: resolver_return65: +// CHECK-NEXT: ret ptr @fmv._Maes +// CHECK: resolver_else66: +// CHECK-NEXT: [[TMP136:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP137:%.*]] = and i64 [[TMP136]], 13056 +// CHECK-NEXT: [[TMP138:%.*]] = icmp eq i64 [[TMP137]], 13056 +// CHECK-NEXT: [[TMP139:%.*]] = and i1 true, [[TMP138]] +// CHECK-NEXT: br i1 [[TMP139]], label [[RESOLVER_RETURN67:%.*]], label [[RESOLVER_ELSE68:%.*]] +// CHECK: resolver_return67: +// CHECK-NEXT: ret ptr @fmv._Msha3 +// CHECK: resolver_else68: +// CHECK-NEXT: [[TMP140:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP141:%.*]] = and i64 [[TMP140]], 4864 +// CHECK-NEXT: [[TMP142:%.*]] = icmp eq i64 [[TMP141]], 4864 +// CHECK-NEXT: [[TMP143:%.*]] = and i1 true, [[TMP142]] +// CHECK-NEXT: br i1 [[TMP143]], label [[RESOLVER_RETURN69:%.*]], label [[RESOLVER_ELSE70:%.*]] +// CHECK: resolver_return69: +// CHECK-NEXT: ret ptr @fmv._Msha2 +// CHECK: resolver_else70: +// CHECK-NEXT: [[TMP144:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP145:%.*]] = and i64 [[TMP144]], 1024 +// CHECK-NEXT: [[TMP146:%.*]] = icmp eq i64 [[TMP145]], 1024 +// CHECK-NEXT: [[TMP147:%.*]] = and i1 true, [[TMP146]] +// CHECK-NEXT: br i1 [[TMP147]], label [[RESOLVER_RETURN71:%.*]], label [[RESOLVER_ELSE72:%.*]] +// CHECK: resolver_return71: +// CHECK-NEXT: ret ptr @fmv._Mcrc +// CHECK: resolver_else72: +// CHECK-NEXT: [[TMP148:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP149:%.*]] = and i64 [[TMP148]], 832 +// CHECK-NEXT: [[TMP150:%.*]] = icmp eq i64 [[TMP149]], 832 +// CHECK-NEXT: [[TMP151:%.*]] = and i1 true, [[TMP150]] +// CHECK-NEXT: br i1 [[TMP151]], label [[RESOLVER_RETURN73:%.*]], label [[RESOLVER_ELSE74:%.*]] +// CHECK: resolver_return73: +// CHECK-NEXT: ret ptr @fmv._Mrdm +// CHECK: resolver_else74: +// CHECK-NEXT: [[TMP152:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP153:%.*]] = and i64 [[TMP152]], 800 +// CHECK-NEXT: [[TMP154:%.*]] = icmp eq i64 [[TMP153]], 800 +// CHECK-NEXT: [[TMP155:%.*]] = and i1 true, [[TMP154]] +// CHECK-NEXT: br i1 [[TMP155]], label [[RESOLVER_RETURN75:%.*]], label [[RESOLVER_ELSE76:%.*]] +// CHECK: resolver_return75: +// CHECK-NEXT: ret ptr @fmv._Msm4 +// CHECK: resolver_else76: +// CHECK-NEXT: [[TMP156:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP157:%.*]] = and i64 [[TMP156]], 784 +// CHECK-NEXT: [[TMP158:%.*]] = icmp eq i64 [[TMP157]], 784 +// CHECK-NEXT: [[TMP159:%.*]] = and i1 true, [[TMP158]] +// CHECK-NEXT: br i1 [[TMP159]], label [[RESOLVER_RETURN77:%.*]], label [[RESOLVER_ELSE78:%.*]] +// CHECK: resolver_return77: +// CHECK-NEXT: ret ptr @fmv._Mdotprod +// CHECK: resolver_else78: +// CHECK-NEXT: [[TMP160:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP161:%.*]] = and i64 [[TMP160]], 768 +// CHECK-NEXT: [[TMP162:%.*]] = icmp eq i64 [[TMP161]], 768 +// CHECK-NEXT: [[TMP163:%.*]] = and i1 true, [[TMP162]] +// CHECK-NEXT: br i1 [[TMP163]], label [[RESOLVER_RETURN79:%.*]], label [[RESOLVER_ELSE80:%.*]] +// CHECK: resolver_return79: +// CHECK-NEXT: ret ptr @fmv._Msimd +// CHECK: resolver_else80: +// CHECK-NEXT: [[TMP164:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP165:%.*]] = and i64 [[TMP164]], 256 +// CHECK-NEXT: [[TMP166:%.*]] = icmp eq i64 [[TMP165]], 256 +// CHECK-NEXT: [[TMP167:%.*]] = and i1 true, [[TMP166]] +// CHECK-NEXT: br i1 [[TMP167]], label [[RESOLVER_RETURN81:%.*]], label [[RESOLVER_ELSE82:%.*]] +// CHECK: resolver_return81: +// CHECK-NEXT: ret ptr @fmv._Mfp +// CHECK: resolver_else82: +// CHECK-NEXT: [[TMP168:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP169:%.*]] = and i64 [[TMP168]], 128 +// CHECK-NEXT: [[TMP170:%.*]] = icmp eq i64 [[TMP169]], 128 +// CHECK-NEXT: [[TMP171:%.*]] = and i1 true, [[TMP170]] +// CHECK-NEXT: br i1 [[TMP171]], label [[RESOLVER_RETURN83:%.*]], label [[RESOLVER_ELSE84:%.*]] +// CHECK: resolver_return83: +// CHECK-NEXT: ret ptr @fmv._Mlse +// CHECK: resolver_else84: +// CHECK-NEXT: [[TMP172:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP173:%.*]] = and i64 [[TMP172]], 6 +// CHECK-NEXT: [[TMP174:%.*]] = icmp eq i64 [[TMP173]], 6 +// CHECK-NEXT: [[TMP175:%.*]] = and i1 true, [[TMP174]] +// CHECK-NEXT: br i1 [[TMP175]], label [[RESOLVER_RETURN85:%.*]], label [[RESOLVER_ELSE86:%.*]] +// CHECK: resolver_return85: +// CHECK-NEXT: ret ptr @fmv._Mflagm2 +// CHECK: resolver_else86: +// CHECK-NEXT: [[TMP176:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP177:%.*]] = and i64 [[TMP176]], 2 +// CHECK-NEXT: [[TMP178:%.*]] = icmp eq i64 [[TMP177]], 2 +// CHECK-NEXT: [[TMP179:%.*]] = and i1 true, [[TMP178]] +// CHECK-NEXT: br i1 [[TMP179]], label [[RESOLVER_RETURN87:%.*]], label [[RESOLVER_ELSE88:%.*]] +// CHECK: resolver_return87: +// CHECK-NEXT: ret ptr @fmv._Mflagm +// CHECK: resolver_else88: +// CHECK-NEXT: [[TMP180:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP181:%.*]] = and i64 [[TMP180]], 1 +// CHECK-NEXT: [[TMP182:%.*]] = icmp eq i64 [[TMP181]], 1 +// CHECK-NEXT: [[TMP183:%.*]] = and i1 true, [[TMP182]] +// CHECK-NEXT: br i1 [[TMP183]], label [[RESOLVER_RETURN89:%.*]], label [[RESOLVER_ELSE90:%.*]] +// CHECK: resolver_return89: +// CHECK-NEXT: ret ptr @fmv._Mrng +// CHECK: resolver_else90: +// CHECK-NEXT: ret ptr @fmv.default // //. // CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4} diff --git a/clang/test/CodeGen/AArch64/fmv-duplicate-mangled-name.c b/clang/test/CodeGen/AArch64/fmv-duplicate-mangled-name.c new file mode 100644 index 0000000000000..e7e611e09542e --- /dev/null +++ b/clang/test/CodeGen/AArch64/fmv-duplicate-mangled-name.c @@ -0,0 +1,24 @@ +// RUN: %clang_cc1 -triple aarch64-linux-gnu -verify -emit-llvm-only %s -DCHECK_IMPLICIT_DEFAULT +// RUN: %clang_cc1 -triple aarch64-linux-gnu -verify -emit-llvm-only %s -DCHECK_EXPLICIT_DEFAULT + +#if defined(CHECK_IMPLICIT_DEFAULT) + +int implicit_default_ok(void) { return 0; } +__attribute__((target_clones("aes", "lse"))) int implicit_default_ok(void) { return 1; } + +int implicit_default_bad(void) { return 0; } +// expected-error@+2 {{definition with same mangled name 'implicit_default_bad.default' as another definition}} +// expected-note@-2 {{previous definition is here}} +__attribute__((target_clones("aes", "lse", "default"))) int implicit_default_bad(void) { return 1; } + +#elif defined(CHECK_EXPLICIT_DEFAULT) + +__attribute__((target_version("default"))) int explicit_default_ok(void) { return 0; } +__attribute__((target_clones("aes", "lse"))) int explicit_default_ok(void) { return 1; } + +__attribute__((target_version("default"))) int explicit_default_bad(void) { return 0; } +// expected-error@+2 {{definition with same mangled name 'explicit_default_bad.default' as another definition}} +// expected-note@-2 {{previous definition is here}} +__attribute__((target_clones("aes", "lse", "default"))) int explicit_default_bad(void) { return 1; } + +#endif diff --git a/clang/test/CodeGen/AArch64/fmv-features.c b/clang/test/CodeGen/AArch64/fmv-features.c index fdc64e2cd395c..f8b5a9b15456f 100644 --- a/clang/test/CodeGen/AArch64/fmv-features.c +++ b/clang/test/CodeGen/AArch64/fmv-features.c @@ -140,7 +140,7 @@ __attribute__((target_version("crc+bti+bti+bti+aes+aes+bf16"))) int fmv(void) { __attribute__((target_version("non_existent_extension"))) int fmv(void); // CHECK: define dso_local i32 @fmv.default() #[[default:[0-9]+]] { -__attribute__((target_version("default"))) int fmv(void); +__attribute__((target_version("default"))) int fmv(void) { return 0; } int caller() { return fmv(); diff --git a/clang/test/CodeGen/AArch64/fmv-resolver-emission.c b/clang/test/CodeGen/AArch64/fmv-resolver-emission.c index 84667910c6e53..591625d4d0da1 100644 --- a/clang/test/CodeGen/AArch64/fmv-resolver-emission.c +++ b/clang/test/CodeGen/AArch64/fmv-resolver-emission.c @@ -68,6 +68,14 @@ inline __attribute__((target_version("default"))) void linkonce_func(void) {} void call_linkonce(void) { linkonce_func(); } +// Test that an ifunc is generated when the clones attribute has a default version. +__attribute__((target_clones("default", "aes"))) void clones_with_default(void) {} + + +// Test that an ifunc is NOT generated when the clones attribute does not have a default version. +__attribute__((target_clones("aes"))) void clones_without_default(void) {} + + //. // CHECK: @__aarch64_cpu_features = external dso_local global { i64 } // CHECK: @used_before_default_def = weak_odr ifunc void (), ptr @used_before_default_def.resolver @@ -76,6 +84,7 @@ void call_linkonce(void) { linkonce_func(); } // CHECK: @indirect_use = weak_odr ifunc void (), ptr @indirect_use.resolver // CHECK: @internal_func = internal ifunc void (), ptr @internal_func.resolver // CHECK: @linkonce_func = weak_odr ifunc void (), ptr @linkonce_func.resolver +// CHECK: @clones_with_default = weak_odr ifunc void (), ptr @clones_with_default.resolver //. // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@used_before_default_def._Maes @@ -228,6 +237,27 @@ void call_linkonce(void) { linkonce_func(); } // CHECK-NEXT: ret void // // +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@clones_with_default.default +// CHECK-SAME: () #[[ATTR2]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret void +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@clones_with_default._Maes +// CHECK-SAME: () #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret void +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@clones_without_default._Maes +// CHECK-SAME: () #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret void +// +// // CHECK-LABEL: define {{[^@]+}}@used_before_default_def.resolver() comdat { // CHECK-NEXT: resolver_entry: // CHECK-NEXT: call void @__init_cpu_features_resolver() @@ -339,6 +369,20 @@ void call_linkonce(void) { linkonce_func(); } // CHECK: resolver_else: // CHECK-NEXT: ret ptr @linkonce_func.default // +// +// CHECK-LABEL: define {{[^@]+}}@clones_with_default.resolver() comdat { +// CHECK-NEXT: resolver_entry: +// CHECK-NEXT: call void @__init_cpu_features_resolver() +// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 33536 +// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 33536 +// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] +// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] +// CHECK: resolver_return: +// CHECK-NEXT: ret ptr @clones_with_default._Maes +// CHECK: resolver_else: +// CHECK-NEXT: ret ptr @clones_with_default.default +// //. // CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4} // CHECK: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"} diff --git a/clang/test/CodeGen/AArch64/mixed-target-attributes.c b/clang/test/CodeGen/AArch64/mixed-target-attributes.c index 1ccb0c6177c8c..ef47c8a3bc737 100644 --- a/clang/test/CodeGen/AArch64/mixed-target-attributes.c +++ b/clang/test/CodeGen/AArch64/mixed-target-attributes.c @@ -4,19 +4,19 @@ // The following is guarded because in NOFMV we get an error for redefining the default. #ifdef __HAVE_FUNCTION_MULTI_VERSIONING -int explicit_default(void) { return 0; } -__attribute__((target_version("jscvt"))) int explicit_default(void) { return 1; } -__attribute__((target_clones("dotprod", "lse"))) int explicit_default(void) { return 2; } -__attribute__((target_version("rdma"))) int explicit_default(void) { return 3; } - -int foo(void) { return explicit_default(); } -#endif - +int implicit_default(void) { return 0; } __attribute__((target_version("jscvt"))) int implicit_default(void) { return 1; } __attribute__((target_clones("dotprod", "lse"))) int implicit_default(void) { return 2; } __attribute__((target_version("rdma"))) int implicit_default(void) { return 3; } -int bar(void) { return implicit_default(); } +int foo(void) { return implicit_default(); } +#endif + +__attribute__((target_version("jscvt"))) int explicit_default(void) { return 1; } +__attribute__((target_clones("dotprod", "lse", "default"))) int explicit_default(void) { return 2; } +__attribute__((target_version("rdma"))) int explicit_default(void) { return 3; } + +int bar(void) { return explicit_default(); } // These shouldn't generate anything. int unused_version_declarations(void); @@ -30,78 +30,40 @@ __attribute__((target_version("jscvt"))) int default_def_with_version_decls(void //. // CHECK: @__aarch64_cpu_features = external dso_local global { i64 } -// CHECK: @explicit_default = weak_odr ifunc i32 (), ptr @explicit_default.resolver // CHECK: @implicit_default = weak_odr ifunc i32 (), ptr @implicit_default.resolver +// CHECK: @explicit_default = weak_odr ifunc i32 (), ptr @explicit_default.resolver // CHECK: @default_def_with_version_decls = weak_odr ifunc i32 (), ptr @default_def_with_version_decls.resolver //. // CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@explicit_default.default +// CHECK-LABEL: define {{[^@]+}}@implicit_default.default // CHECK-SAME: () #[[ATTR0:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 0 // // // CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@explicit_default._Mjscvt +// CHECK-LABEL: define {{[^@]+}}@implicit_default._Mjscvt // CHECK-SAME: () #[[ATTR1:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 1 // // // CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@explicit_default._Mdotprod +// CHECK-LABEL: define {{[^@]+}}@implicit_default._Mdotprod // CHECK-SAME: () #[[ATTR2:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 2 // // // CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@explicit_default._Mlse +// CHECK-LABEL: define {{[^@]+}}@implicit_default._Mlse // CHECK-SAME: () #[[ATTR3:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 2 // // -// CHECK-LABEL: define {{[^@]+}}@explicit_default.resolver() comdat { -// CHECK-NEXT: resolver_entry: -// CHECK-NEXT: call void @__init_cpu_features_resolver() -// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1048832 -// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1048832 -// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] -// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] -// CHECK: resolver_return: -// CHECK-NEXT: ret ptr @explicit_default._Mjscvt -// CHECK: resolver_else: -// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 832 -// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 832 -// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] -// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] -// CHECK: resolver_return1: -// CHECK-NEXT: ret ptr @explicit_default._Mrdm -// CHECK: resolver_else2: -// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 784 -// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 784 -// CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]] -// CHECK-NEXT: br i1 [[TMP11]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]] -// CHECK: resolver_return3: -// CHECK-NEXT: ret ptr @explicit_default._Mdotprod -// CHECK: resolver_else4: -// CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP13:%.*]] = and i64 [[TMP12]], 128 -// CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[TMP13]], 128 -// CHECK-NEXT: [[TMP15:%.*]] = and i1 true, [[TMP14]] -// CHECK-NEXT: br i1 [[TMP15]], label [[RESOLVER_RETURN5:%.*]], label [[RESOLVER_ELSE6:%.*]] -// CHECK: resolver_return5: -// CHECK-NEXT: ret ptr @explicit_default._Mlse -// CHECK: resolver_else6: -// CHECK-NEXT: ret ptr @explicit_default.default -// -// // CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@explicit_default._Mrdm +// CHECK-LABEL: define {{[^@]+}}@implicit_default._Mrdm // CHECK-SAME: () #[[ATTR4:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 3 @@ -111,31 +73,60 @@ __attribute__((target_version("jscvt"))) int default_def_with_version_decls(void // CHECK-LABEL: define {{[^@]+}}@foo // CHECK-SAME: () #[[ATTR0]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[CALL:%.*]] = call i32 @explicit_default() +// CHECK-NEXT: [[CALL:%.*]] = call i32 @implicit_default() // CHECK-NEXT: ret i32 [[CALL]] // // // CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@implicit_default._Mjscvt +// CHECK-LABEL: define {{[^@]+}}@explicit_default._Mjscvt // CHECK-SAME: () #[[ATTR1]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 1 // // // CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@implicit_default._Mdotprod +// CHECK-LABEL: define {{[^@]+}}@explicit_default._Mdotprod // CHECK-SAME: () #[[ATTR2]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 2 // // // CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@implicit_default._Mlse +// CHECK-LABEL: define {{[^@]+}}@explicit_default._Mlse // CHECK-SAME: () #[[ATTR3]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 2 // // +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@explicit_default.default +// CHECK-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 2 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@explicit_default._Mrdm +// CHECK-SAME: () #[[ATTR4]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 3 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@bar +// CHECK-SAME: () #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[CALL:%.*]] = call i32 @explicit_default() +// CHECK-NEXT: ret i32 [[CALL]] +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@default_def_with_version_decls.default +// CHECK-SAME: () #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// // CHECK-LABEL: define {{[^@]+}}@implicit_default.resolver() comdat { // CHECK-NEXT: resolver_entry: // CHECK-NEXT: call void @__init_cpu_features_resolver() @@ -174,33 +165,42 @@ __attribute__((target_version("jscvt"))) int default_def_with_version_decls(void // CHECK-NEXT: ret ptr @implicit_default.default // // -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@implicit_default._Mrdm -// CHECK-SAME: () #[[ATTR4]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 3 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@bar -// CHECK-SAME: () #[[ATTR0]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[CALL:%.*]] = call i32 @implicit_default() -// CHECK-NEXT: ret i32 [[CALL]] -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@default_def_with_version_decls.default -// CHECK-SAME: () #[[ATTR0]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 0 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@implicit_default.default -// CHECK-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 2 +// CHECK-LABEL: define {{[^@]+}}@explicit_default.resolver() comdat { +// CHECK-NEXT: resolver_entry: +// CHECK-NEXT: call void @__init_cpu_features_resolver() +// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1048832 +// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1048832 +// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] +// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] +// CHECK: resolver_return: +// CHECK-NEXT: ret ptr @explicit_default._Mjscvt +// CHECK: resolver_else: +// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 832 +// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 832 +// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] +// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] +// CHECK: resolver_return1: +// CHECK-NEXT: ret ptr @explicit_default._Mrdm +// CHECK: resolver_else2: +// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 784 +// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 784 +// CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]] +// CHECK-NEXT: br i1 [[TMP11]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]] +// CHECK: resolver_return3: +// CHECK-NEXT: ret ptr @explicit_default._Mdotprod +// CHECK: resolver_else4: +// CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP13:%.*]] = and i64 [[TMP12]], 128 +// CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[TMP13]], 128 +// CHECK-NEXT: [[TMP15:%.*]] = and i1 true, [[TMP14]] +// CHECK-NEXT: br i1 [[TMP15]], label [[RESOLVER_RETURN5:%.*]], label [[RESOLVER_ELSE6:%.*]] +// CHECK: resolver_return5: +// CHECK-NEXT: ret ptr @explicit_default._Mlse +// CHECK: resolver_else6: +// CHECK-NEXT: ret ptr @explicit_default.default // // // CHECK-LABEL: define {{[^@]+}}@default_def_with_version_decls.resolver() comdat { @@ -234,7 +234,7 @@ __attribute__((target_version("jscvt"))) int default_def_with_version_decls(void // // // CHECK-NOFMV: Function Attrs: noinline nounwind optnone -// CHECK-NOFMV-LABEL: define {{[^@]+}}@implicit_default +// CHECK-NOFMV-LABEL: define {{[^@]+}}@explicit_default // CHECK-NOFMV-SAME: () #[[ATTR0:[0-9]+]] { // CHECK-NOFMV-NEXT: entry: // CHECK-NOFMV-NEXT: ret i32 2 @@ -244,7 +244,7 @@ __attribute__((target_version("jscvt"))) int default_def_with_version_decls(void // CHECK-NOFMV-LABEL: define {{[^@]+}}@bar // CHECK-NOFMV-SAME: () #[[ATTR0]] { // CHECK-NOFMV-NEXT: entry: -// CHECK-NOFMV-NEXT: [[CALL:%.*]] = call i32 @implicit_default() +// CHECK-NOFMV-NEXT: [[CALL:%.*]] = call i32 @explicit_default() // CHECK-NOFMV-NEXT: ret i32 [[CALL]] // // diff --git a/clang/test/CodeGen/attr-target-clones-aarch64.c b/clang/test/CodeGen/attr-target-clones-aarch64.c index ac926f2329cc4..57add8b8c8abc 100644 --- a/clang/test/CodeGen/attr-target-clones-aarch64.c +++ b/clang/test/CodeGen/attr-target-clones-aarch64.c @@ -6,15 +6,15 @@ int __attribute__((target_clones("lse+aes", "sve2"))) ftc(void) { return 0; } int __attribute__((target_clones("sha2", "sha2+memtag", " default "))) ftc_def(void) { return 1; } int __attribute__((target_clones("sha2", "default"))) ftc_dup1(void) { return 2; } -int __attribute__((target_clones("fp", "crc+dotprod"))) ftc_dup2(void) { return 3; } -int __attribute__((target_clones("memtag", "bti"))) ftc_dup3(void) { return 4; } +int __attribute__((target_clones("fp", "crc+dotprod", "default"))) ftc_dup2(void) { return 3; } +int __attribute__((target_clones("memtag", "bti", "default"))) ftc_dup3(void) { return 4; } int foo() { return ftc() + ftc_def() + ftc_dup1() + ftc_dup2() + ftc_dup3(); } inline int __attribute__((target_clones("rng+simd", "rcpc", "sve2-aes+wfxt"))) ftc_inline1(void) { return 1; } inline int __attribute__((target_clones("fp16", "fcma+sve2-bitperm", "default"))) ftc_inline2(void); -inline int __attribute__((target_clones("bti", "sve+sb"))) ftc_inline3(void) { return 3; } +inline int __attribute__((target_clones("bti", "sve+sb", "default"))) ftc_inline3(void) { return 3; } int __attribute__((target_clones("default"))) ftc_direct(void) { return 4; } @@ -27,23 +27,19 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default")) //. // CHECK: @__aarch64_cpu_features = external dso_local global { i64 } -// CHECK: @ftc = weak_odr ifunc i32 (), ptr @ftc.resolver // CHECK: @ftc_def = weak_odr ifunc i32 (), ptr @ftc_def.resolver // CHECK: @ftc_dup1 = weak_odr ifunc i32 (), ptr @ftc_dup1.resolver // CHECK: @ftc_dup2 = weak_odr ifunc i32 (), ptr @ftc_dup2.resolver // CHECK: @ftc_dup3 = weak_odr ifunc i32 (), ptr @ftc_dup3.resolver // CHECK: @ftc_inline2 = weak_odr ifunc i32 (), ptr @ftc_inline2.resolver -// CHECK: @ftc_inline1 = weak_odr ifunc i32 (), ptr @ftc_inline1.resolver // CHECK: @ftc_inline3 = weak_odr ifunc i32 (), ptr @ftc_inline3.resolver //. // CHECK-MTE-BTI: @__aarch64_cpu_features = external dso_local global { i64 } -// CHECK-MTE-BTI: @ftc = weak_odr ifunc i32 (), ptr @ftc.resolver // CHECK-MTE-BTI: @ftc_def = weak_odr ifunc i32 (), ptr @ftc_def.resolver // CHECK-MTE-BTI: @ftc_dup1 = weak_odr ifunc i32 (), ptr @ftc_dup1.resolver // CHECK-MTE-BTI: @ftc_dup2 = weak_odr ifunc i32 (), ptr @ftc_dup2.resolver // CHECK-MTE-BTI: @ftc_dup3 = weak_odr ifunc i32 (), ptr @ftc_dup3.resolver // CHECK-MTE-BTI: @ftc_inline2 = weak_odr ifunc i32 (), ptr @ftc_inline2.resolver -// CHECK-MTE-BTI: @ftc_inline1 = weak_odr ifunc i32 (), ptr @ftc_inline1.resolver // CHECK-MTE-BTI: @ftc_inline3 = weak_odr ifunc i32 (), ptr @ftc_inline3.resolver //. // CHECK: Function Attrs: noinline nounwind optnone @@ -60,28 +56,6 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default")) // CHECK-NEXT: ret i32 0 // // -// CHECK-LABEL: define {{[^@]+}}@ftc.resolver() comdat { -// CHECK-NEXT: resolver_entry: -// CHECK-NEXT: call void @__init_cpu_features_resolver() -// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 69793284352 -// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 69793284352 -// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] -// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] -// CHECK: resolver_return: -// CHECK-NEXT: ret ptr @ftc._Msve2 -// CHECK: resolver_else: -// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 33664 -// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 33664 -// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] -// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] -// CHECK: resolver_return1: -// CHECK-NEXT: ret ptr @ftc._MaesMlse -// CHECK: resolver_else2: -// CHECK-NEXT: ret ptr @ftc.default -// -// // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@ftc_def._Msha2 // CHECK-SAME: () #[[ATTR2:[0-9]+]] { @@ -96,26 +70,11 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default")) // CHECK-NEXT: ret i32 1 // // -// CHECK-LABEL: define {{[^@]+}}@ftc_def.resolver() comdat { -// CHECK-NEXT: resolver_entry: -// CHECK-NEXT: call void @__init_cpu_features_resolver() -// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 17592186049280 -// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 17592186049280 -// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] -// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] -// CHECK: resolver_return: -// CHECK-NEXT: ret ptr @ftc_def._MmemtagMsha2 -// CHECK: resolver_else: -// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 4864 -// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 4864 -// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] -// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] -// CHECK: resolver_return1: -// CHECK-NEXT: ret ptr @ftc_def._Msha2 -// CHECK: resolver_else2: -// CHECK-NEXT: ret ptr @ftc_def.default +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@ftc_def.default +// CHECK-SAME: () #[[ATTR4:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 // // // CHECK: Function Attrs: noinline nounwind optnone @@ -125,95 +84,58 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default")) // CHECK-NEXT: ret i32 2 // // -// CHECK-LABEL: define {{[^@]+}}@ftc_dup1.resolver() comdat { -// CHECK-NEXT: resolver_entry: -// CHECK-NEXT: call void @__init_cpu_features_resolver() -// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 4864 -// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 4864 -// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] -// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] -// CHECK: resolver_return: -// CHECK-NEXT: ret ptr @ftc_dup1._Msha2 -// CHECK: resolver_else: -// CHECK-NEXT: ret ptr @ftc_dup1.default +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@ftc_dup1.default +// CHECK-SAME: () #[[ATTR4]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 2 // // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@ftc_dup2._Mfp -// CHECK-SAME: () #[[ATTR4:[0-9]+]] { +// CHECK-SAME: () #[[ATTR5:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 3 // // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@ftc_dup2._McrcMdotprod -// CHECK-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK-SAME: () #[[ATTR6:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 3 // // -// CHECK-LABEL: define {{[^@]+}}@ftc_dup2.resolver() comdat { -// CHECK-NEXT: resolver_entry: -// CHECK-NEXT: call void @__init_cpu_features_resolver() -// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1808 -// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1808 -// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] -// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] -// CHECK: resolver_return: -// CHECK-NEXT: ret ptr @ftc_dup2._McrcMdotprod -// CHECK: resolver_else: -// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 256 -// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 256 -// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] -// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] -// CHECK: resolver_return1: -// CHECK-NEXT: ret ptr @ftc_dup2._Mfp -// CHECK: resolver_else2: -// CHECK-NEXT: ret ptr @ftc_dup2.default +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@ftc_dup2.default +// CHECK-SAME: () #[[ATTR4]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 3 // // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@ftc_dup3._Mmemtag -// CHECK-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK-SAME: () #[[ATTR7:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 4 // // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@ftc_dup3._Mbti -// CHECK-SAME: () #[[ATTR7:[0-9]+]] { +// CHECK-SAME: () #[[ATTR8:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 4 // // -// CHECK-LABEL: define {{[^@]+}}@ftc_dup3.resolver() comdat { -// CHECK-NEXT: resolver_entry: -// CHECK-NEXT: call void @__init_cpu_features_resolver() -// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1125899906842624 -// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1125899906842624 -// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] -// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] -// CHECK: resolver_return: -// CHECK-NEXT: ret ptr @ftc_dup3._Mbti -// CHECK: resolver_else: -// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 17592186044416 -// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 17592186044416 -// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] -// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] -// CHECK: resolver_return1: -// CHECK-NEXT: ret ptr @ftc_dup3._Mmemtag -// CHECK: resolver_else2: -// CHECK-NEXT: ret ptr @ftc_dup3.default +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@ftc_dup3.default +// CHECK-SAME: () #[[ATTR4]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 4 // // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@foo -// CHECK-SAME: () #[[ATTR8:[0-9]+]] { +// CHECK-SAME: () #[[ATTR9:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[CALL:%.*]] = call i32 @ftc() // CHECK-NEXT: [[CALL1:%.*]] = call i32 @ftc_def() @@ -229,14 +151,14 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default")) // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@ftc_direct -// CHECK-SAME: () #[[ATTR8]] { +// CHECK-SAME: () #[[ATTR9]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 4 // // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@main -// CHECK-SAME: () #[[ATTR8]] { +// CHECK-SAME: () #[[ATTR9]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK-NEXT: store i32 0, ptr [[RETVAL]], align 4 @@ -250,58 +172,103 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default")) // CHECK-NEXT: ret i32 [[ADD5]] // // -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@ftc.default -// CHECK-SAME: () #[[ATTR9:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 0 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@ftc_def.default -// CHECK-SAME: () #[[ATTR9]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 +// CHECK-LABEL: define {{[^@]+}}@ftc_def.resolver() comdat { +// CHECK-NEXT: resolver_entry: +// CHECK-NEXT: call void @__init_cpu_features_resolver() +// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 17592186049280 +// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 17592186049280 +// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] +// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] +// CHECK: resolver_return: +// CHECK-NEXT: ret ptr @ftc_def._MmemtagMsha2 +// CHECK: resolver_else: +// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 4864 +// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 4864 +// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] +// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] +// CHECK: resolver_return1: +// CHECK-NEXT: ret ptr @ftc_def._Msha2 +// CHECK: resolver_else2: +// CHECK-NEXT: ret ptr @ftc_def.default // // -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@ftc_dup1.default -// CHECK-SAME: () #[[ATTR9]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 2 +// CHECK-LABEL: define {{[^@]+}}@ftc_dup1.resolver() comdat { +// CHECK-NEXT: resolver_entry: +// CHECK-NEXT: call void @__init_cpu_features_resolver() +// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 4864 +// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 4864 +// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] +// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] +// CHECK: resolver_return: +// CHECK-NEXT: ret ptr @ftc_dup1._Msha2 +// CHECK: resolver_else: +// CHECK-NEXT: ret ptr @ftc_dup1.default // // -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@ftc_dup2.default -// CHECK-SAME: () #[[ATTR9]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 3 +// CHECK-LABEL: define {{[^@]+}}@ftc_dup2.resolver() comdat { +// CHECK-NEXT: resolver_entry: +// CHECK-NEXT: call void @__init_cpu_features_resolver() +// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1808 +// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1808 +// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] +// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] +// CHECK: resolver_return: +// CHECK-NEXT: ret ptr @ftc_dup2._McrcMdotprod +// CHECK: resolver_else: +// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 256 +// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 256 +// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] +// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] +// CHECK: resolver_return1: +// CHECK-NEXT: ret ptr @ftc_dup2._Mfp +// CHECK: resolver_else2: +// CHECK-NEXT: ret ptr @ftc_dup2.default // // -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@ftc_dup3.default -// CHECK-SAME: () #[[ATTR9]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 4 +// CHECK-LABEL: define {{[^@]+}}@ftc_dup3.resolver() comdat { +// CHECK-NEXT: resolver_entry: +// CHECK-NEXT: call void @__init_cpu_features_resolver() +// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1125899906842624 +// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1125899906842624 +// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] +// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] +// CHECK: resolver_return: +// CHECK-NEXT: ret ptr @ftc_dup3._Mbti +// CHECK: resolver_else: +// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 17592186044416 +// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 17592186044416 +// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] +// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] +// CHECK: resolver_return1: +// CHECK-NEXT: ret ptr @ftc_dup3._Mmemtag +// CHECK: resolver_else2: +// CHECK-NEXT: ret ptr @ftc_dup3.default // // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@ftc_inline2._Mfp16 -// CHECK-SAME: () #[[ATTR10:[0-9]+]] { +// CHECK-SAME: () #[[ATTR12:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 2 // // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@ftc_inline2._MfcmaMsve2-bitperm -// CHECK-SAME: () #[[ATTR11:[0-9]+]] { +// CHECK-SAME: () #[[ATTR13:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 2 // // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@ftc_inline2.default -// CHECK-SAME: () #[[ATTR9]] { +// CHECK-SAME: () #[[ATTR4]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 2 // @@ -330,79 +297,42 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default")) // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@ftc_inline1._MrngMsimd -// CHECK-SAME: () #[[ATTR12:[0-9]+]] { +// CHECK-SAME: () #[[ATTR14:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 1 // // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@ftc_inline1._Mrcpc -// CHECK-SAME: () #[[ATTR13:[0-9]+]] { +// CHECK-SAME: () #[[ATTR15:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 1 // // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@ftc_inline1._Msve2-aesMwfxt -// CHECK-SAME: () #[[ATTR14:[0-9]+]] { +// CHECK-SAME: () #[[ATTR16:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 1 // // // CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@ftc_inline1.default -// CHECK-SAME: () #[[ATTR9]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define {{[^@]+}}@ftc_inline1.resolver() comdat { -// CHECK-NEXT: resolver_entry: -// CHECK-NEXT: call void @__init_cpu_features_resolver() -// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 18014743180706560 -// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 18014743180706560 -// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] -// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] -// CHECK: resolver_return: -// CHECK-NEXT: ret ptr @ftc_inline1._Msve2-aesMwfxt -// CHECK: resolver_else: -// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 4194304 -// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 4194304 -// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] -// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] -// CHECK: resolver_return1: -// CHECK-NEXT: ret ptr @ftc_inline1._Mrcpc -// CHECK: resolver_else2: -// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 769 -// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 769 -// CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]] -// CHECK-NEXT: br i1 [[TMP11]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]] -// CHECK: resolver_return3: -// CHECK-NEXT: ret ptr @ftc_inline1._MrngMsimd -// CHECK: resolver_else4: -// CHECK-NEXT: ret ptr @ftc_inline1.default -// -// -// CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@ftc_inline3._Mbti -// CHECK-SAME: () #[[ATTR7]] { +// CHECK-SAME: () #[[ATTR8]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 3 // // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@ftc_inline3._MsbMsve -// CHECK-SAME: () #[[ATTR15:[0-9]+]] { +// CHECK-SAME: () #[[ATTR17:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 3 // // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@ftc_inline3.default -// CHECK-SAME: () #[[ATTR9]] { +// CHECK-SAME: () #[[ATTR4]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 3 // @@ -517,28 +447,6 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default")) // CHECK-MTE-BTI-NEXT: ret i32 0 // // -// CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc.resolver() comdat { -// CHECK-MTE-BTI-NEXT: resolver_entry: -// CHECK-MTE-BTI-NEXT: call void @__init_cpu_features_resolver() -// CHECK-MTE-BTI-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-MTE-BTI-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 69793284352 -// CHECK-MTE-BTI-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 69793284352 -// CHECK-MTE-BTI-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] -// CHECK-MTE-BTI-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] -// CHECK-MTE-BTI: resolver_return: -// CHECK-MTE-BTI-NEXT: ret ptr @ftc._Msve2 -// CHECK-MTE-BTI: resolver_else: -// CHECK-MTE-BTI-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-MTE-BTI-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 33664 -// CHECK-MTE-BTI-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 33664 -// CHECK-MTE-BTI-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] -// CHECK-MTE-BTI-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] -// CHECK-MTE-BTI: resolver_return1: -// CHECK-MTE-BTI-NEXT: ret ptr @ftc._MaesMlse -// CHECK-MTE-BTI: resolver_else2: -// CHECK-MTE-BTI-NEXT: ret ptr @ftc.default -// -// // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_def._Msha2 // CHECK-MTE-BTI-SAME: () #[[ATTR2:[0-9]+]] { @@ -553,26 +461,11 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default")) // CHECK-MTE-BTI-NEXT: ret i32 1 // // -// CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_def.resolver() comdat { -// CHECK-MTE-BTI-NEXT: resolver_entry: -// CHECK-MTE-BTI-NEXT: call void @__init_cpu_features_resolver() -// CHECK-MTE-BTI-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-MTE-BTI-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 17592186049280 -// CHECK-MTE-BTI-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 17592186049280 -// CHECK-MTE-BTI-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] -// CHECK-MTE-BTI-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] -// CHECK-MTE-BTI: resolver_return: -// CHECK-MTE-BTI-NEXT: ret ptr @ftc_def._MmemtagMsha2 -// CHECK-MTE-BTI: resolver_else: -// CHECK-MTE-BTI-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-MTE-BTI-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 4864 -// CHECK-MTE-BTI-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 4864 -// CHECK-MTE-BTI-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] -// CHECK-MTE-BTI-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] -// CHECK-MTE-BTI: resolver_return1: -// CHECK-MTE-BTI-NEXT: ret ptr @ftc_def._Msha2 -// CHECK-MTE-BTI: resolver_else2: -// CHECK-MTE-BTI-NEXT: ret ptr @ftc_def.default +// CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone +// CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_def.default +// CHECK-MTE-BTI-SAME: () #[[ATTR4:[0-9]+]] { +// CHECK-MTE-BTI-NEXT: entry: +// CHECK-MTE-BTI-NEXT: ret i32 1 // // // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone @@ -582,95 +475,58 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default")) // CHECK-MTE-BTI-NEXT: ret i32 2 // // -// CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_dup1.resolver() comdat { -// CHECK-MTE-BTI-NEXT: resolver_entry: -// CHECK-MTE-BTI-NEXT: call void @__init_cpu_features_resolver() -// CHECK-MTE-BTI-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-MTE-BTI-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 4864 -// CHECK-MTE-BTI-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 4864 -// CHECK-MTE-BTI-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] -// CHECK-MTE-BTI-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] -// CHECK-MTE-BTI: resolver_return: -// CHECK-MTE-BTI-NEXT: ret ptr @ftc_dup1._Msha2 -// CHECK-MTE-BTI: resolver_else: -// CHECK-MTE-BTI-NEXT: ret ptr @ftc_dup1.default +// CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone +// CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_dup1.default +// CHECK-MTE-BTI-SAME: () #[[ATTR4]] { +// CHECK-MTE-BTI-NEXT: entry: +// CHECK-MTE-BTI-NEXT: ret i32 2 // // // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_dup2._Mfp -// CHECK-MTE-BTI-SAME: () #[[ATTR4:[0-9]+]] { +// CHECK-MTE-BTI-SAME: () #[[ATTR5:[0-9]+]] { // CHECK-MTE-BTI-NEXT: entry: // CHECK-MTE-BTI-NEXT: ret i32 3 // // // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_dup2._McrcMdotprod -// CHECK-MTE-BTI-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK-MTE-BTI-SAME: () #[[ATTR6:[0-9]+]] { // CHECK-MTE-BTI-NEXT: entry: // CHECK-MTE-BTI-NEXT: ret i32 3 // // -// CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_dup2.resolver() comdat { -// CHECK-MTE-BTI-NEXT: resolver_entry: -// CHECK-MTE-BTI-NEXT: call void @__init_cpu_features_resolver() -// CHECK-MTE-BTI-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-MTE-BTI-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1808 -// CHECK-MTE-BTI-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1808 -// CHECK-MTE-BTI-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] -// CHECK-MTE-BTI-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] -// CHECK-MTE-BTI: resolver_return: -// CHECK-MTE-BTI-NEXT: ret ptr @ftc_dup2._McrcMdotprod -// CHECK-MTE-BTI: resolver_else: -// CHECK-MTE-BTI-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-MTE-BTI-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 256 -// CHECK-MTE-BTI-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 256 -// CHECK-MTE-BTI-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] -// CHECK-MTE-BTI-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] -// CHECK-MTE-BTI: resolver_return1: -// CHECK-MTE-BTI-NEXT: ret ptr @ftc_dup2._Mfp -// CHECK-MTE-BTI: resolver_else2: -// CHECK-MTE-BTI-NEXT: ret ptr @ftc_dup2.default +// CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone +// CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_dup2.default +// CHECK-MTE-BTI-SAME: () #[[ATTR4]] { +// CHECK-MTE-BTI-NEXT: entry: +// CHECK-MTE-BTI-NEXT: ret i32 3 // // // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_dup3._Mmemtag -// CHECK-MTE-BTI-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK-MTE-BTI-SAME: () #[[ATTR7:[0-9]+]] { // CHECK-MTE-BTI-NEXT: entry: // CHECK-MTE-BTI-NEXT: ret i32 4 // // // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_dup3._Mbti -// CHECK-MTE-BTI-SAME: () #[[ATTR7:[0-9]+]] { +// CHECK-MTE-BTI-SAME: () #[[ATTR8:[0-9]+]] { // CHECK-MTE-BTI-NEXT: entry: // CHECK-MTE-BTI-NEXT: ret i32 4 // // -// CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_dup3.resolver() comdat { -// CHECK-MTE-BTI-NEXT: resolver_entry: -// CHECK-MTE-BTI-NEXT: call void @__init_cpu_features_resolver() -// CHECK-MTE-BTI-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-MTE-BTI-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1125899906842624 -// CHECK-MTE-BTI-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1125899906842624 -// CHECK-MTE-BTI-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] -// CHECK-MTE-BTI-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] -// CHECK-MTE-BTI: resolver_return: -// CHECK-MTE-BTI-NEXT: ret ptr @ftc_dup3._Mbti -// CHECK-MTE-BTI: resolver_else: -// CHECK-MTE-BTI-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-MTE-BTI-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 17592186044416 -// CHECK-MTE-BTI-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 17592186044416 -// CHECK-MTE-BTI-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] -// CHECK-MTE-BTI-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] -// CHECK-MTE-BTI: resolver_return1: -// CHECK-MTE-BTI-NEXT: ret ptr @ftc_dup3._Mmemtag -// CHECK-MTE-BTI: resolver_else2: -// CHECK-MTE-BTI-NEXT: ret ptr @ftc_dup3.default +// CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone +// CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_dup3.default +// CHECK-MTE-BTI-SAME: () #[[ATTR4]] { +// CHECK-MTE-BTI-NEXT: entry: +// CHECK-MTE-BTI-NEXT: ret i32 4 // // // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@foo -// CHECK-MTE-BTI-SAME: () #[[ATTR8:[0-9]+]] { +// CHECK-MTE-BTI-SAME: () #[[ATTR9:[0-9]+]] { // CHECK-MTE-BTI-NEXT: entry: // CHECK-MTE-BTI-NEXT: [[CALL:%.*]] = call i32 @ftc() // CHECK-MTE-BTI-NEXT: [[CALL1:%.*]] = call i32 @ftc_def() @@ -686,14 +542,14 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default")) // // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_direct -// CHECK-MTE-BTI-SAME: () #[[ATTR8]] { +// CHECK-MTE-BTI-SAME: () #[[ATTR9]] { // CHECK-MTE-BTI-NEXT: entry: // CHECK-MTE-BTI-NEXT: ret i32 4 // // // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@main -// CHECK-MTE-BTI-SAME: () #[[ATTR8]] { +// CHECK-MTE-BTI-SAME: () #[[ATTR9]] { // CHECK-MTE-BTI-NEXT: entry: // CHECK-MTE-BTI-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK-MTE-BTI-NEXT: store i32 0, ptr [[RETVAL]], align 4 @@ -707,58 +563,103 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default")) // CHECK-MTE-BTI-NEXT: ret i32 [[ADD5]] // // -// CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone -// CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc.default -// CHECK-MTE-BTI-SAME: () #[[ATTR9:[0-9]+]] { -// CHECK-MTE-BTI-NEXT: entry: -// CHECK-MTE-BTI-NEXT: ret i32 0 -// -// -// CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone -// CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_def.default -// CHECK-MTE-BTI-SAME: () #[[ATTR9]] { -// CHECK-MTE-BTI-NEXT: entry: -// CHECK-MTE-BTI-NEXT: ret i32 1 +// CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_def.resolver() comdat { +// CHECK-MTE-BTI-NEXT: resolver_entry: +// CHECK-MTE-BTI-NEXT: call void @__init_cpu_features_resolver() +// CHECK-MTE-BTI-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-MTE-BTI-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 17592186049280 +// CHECK-MTE-BTI-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 17592186049280 +// CHECK-MTE-BTI-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] +// CHECK-MTE-BTI-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] +// CHECK-MTE-BTI: resolver_return: +// CHECK-MTE-BTI-NEXT: ret ptr @ftc_def._MmemtagMsha2 +// CHECK-MTE-BTI: resolver_else: +// CHECK-MTE-BTI-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-MTE-BTI-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 4864 +// CHECK-MTE-BTI-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 4864 +// CHECK-MTE-BTI-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] +// CHECK-MTE-BTI-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] +// CHECK-MTE-BTI: resolver_return1: +// CHECK-MTE-BTI-NEXT: ret ptr @ftc_def._Msha2 +// CHECK-MTE-BTI: resolver_else2: +// CHECK-MTE-BTI-NEXT: ret ptr @ftc_def.default // // -// CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone -// CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_dup1.default -// CHECK-MTE-BTI-SAME: () #[[ATTR9]] { -// CHECK-MTE-BTI-NEXT: entry: -// CHECK-MTE-BTI-NEXT: ret i32 2 +// CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_dup1.resolver() comdat { +// CHECK-MTE-BTI-NEXT: resolver_entry: +// CHECK-MTE-BTI-NEXT: call void @__init_cpu_features_resolver() +// CHECK-MTE-BTI-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-MTE-BTI-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 4864 +// CHECK-MTE-BTI-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 4864 +// CHECK-MTE-BTI-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] +// CHECK-MTE-BTI-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] +// CHECK-MTE-BTI: resolver_return: +// CHECK-MTE-BTI-NEXT: ret ptr @ftc_dup1._Msha2 +// CHECK-MTE-BTI: resolver_else: +// CHECK-MTE-BTI-NEXT: ret ptr @ftc_dup1.default // // -// CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone -// CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_dup2.default -// CHECK-MTE-BTI-SAME: () #[[ATTR9]] { -// CHECK-MTE-BTI-NEXT: entry: -// CHECK-MTE-BTI-NEXT: ret i32 3 +// CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_dup2.resolver() comdat { +// CHECK-MTE-BTI-NEXT: resolver_entry: +// CHECK-MTE-BTI-NEXT: call void @__init_cpu_features_resolver() +// CHECK-MTE-BTI-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-MTE-BTI-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1808 +// CHECK-MTE-BTI-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1808 +// CHECK-MTE-BTI-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] +// CHECK-MTE-BTI-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] +// CHECK-MTE-BTI: resolver_return: +// CHECK-MTE-BTI-NEXT: ret ptr @ftc_dup2._McrcMdotprod +// CHECK-MTE-BTI: resolver_else: +// CHECK-MTE-BTI-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-MTE-BTI-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 256 +// CHECK-MTE-BTI-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 256 +// CHECK-MTE-BTI-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] +// CHECK-MTE-BTI-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] +// CHECK-MTE-BTI: resolver_return1: +// CHECK-MTE-BTI-NEXT: ret ptr @ftc_dup2._Mfp +// CHECK-MTE-BTI: resolver_else2: +// CHECK-MTE-BTI-NEXT: ret ptr @ftc_dup2.default // // -// CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone -// CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_dup3.default -// CHECK-MTE-BTI-SAME: () #[[ATTR9]] { -// CHECK-MTE-BTI-NEXT: entry: -// CHECK-MTE-BTI-NEXT: ret i32 4 +// CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_dup3.resolver() comdat { +// CHECK-MTE-BTI-NEXT: resolver_entry: +// CHECK-MTE-BTI-NEXT: call void @__init_cpu_features_resolver() +// CHECK-MTE-BTI-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-MTE-BTI-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1125899906842624 +// CHECK-MTE-BTI-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1125899906842624 +// CHECK-MTE-BTI-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] +// CHECK-MTE-BTI-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] +// CHECK-MTE-BTI: resolver_return: +// CHECK-MTE-BTI-NEXT: ret ptr @ftc_dup3._Mbti +// CHECK-MTE-BTI: resolver_else: +// CHECK-MTE-BTI-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-MTE-BTI-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 17592186044416 +// CHECK-MTE-BTI-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 17592186044416 +// CHECK-MTE-BTI-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] +// CHECK-MTE-BTI-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] +// CHECK-MTE-BTI: resolver_return1: +// CHECK-MTE-BTI-NEXT: ret ptr @ftc_dup3._Mmemtag +// CHECK-MTE-BTI: resolver_else2: +// CHECK-MTE-BTI-NEXT: ret ptr @ftc_dup3.default // // // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_inline2._Mfp16 -// CHECK-MTE-BTI-SAME: () #[[ATTR10:[0-9]+]] { +// CHECK-MTE-BTI-SAME: () #[[ATTR12:[0-9]+]] { // CHECK-MTE-BTI-NEXT: entry: // CHECK-MTE-BTI-NEXT: ret i32 2 // // // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_inline2._MfcmaMsve2-bitperm -// CHECK-MTE-BTI-SAME: () #[[ATTR11:[0-9]+]] { +// CHECK-MTE-BTI-SAME: () #[[ATTR13:[0-9]+]] { // CHECK-MTE-BTI-NEXT: entry: // CHECK-MTE-BTI-NEXT: ret i32 2 // // // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_inline2.default -// CHECK-MTE-BTI-SAME: () #[[ATTR9]] { +// CHECK-MTE-BTI-SAME: () #[[ATTR4]] { // CHECK-MTE-BTI-NEXT: entry: // CHECK-MTE-BTI-NEXT: ret i32 2 // @@ -787,79 +688,42 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default")) // // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_inline1._MrngMsimd -// CHECK-MTE-BTI-SAME: () #[[ATTR12:[0-9]+]] { +// CHECK-MTE-BTI-SAME: () #[[ATTR14:[0-9]+]] { // CHECK-MTE-BTI-NEXT: entry: // CHECK-MTE-BTI-NEXT: ret i32 1 // // // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_inline1._Mrcpc -// CHECK-MTE-BTI-SAME: () #[[ATTR13:[0-9]+]] { +// CHECK-MTE-BTI-SAME: () #[[ATTR15:[0-9]+]] { // CHECK-MTE-BTI-NEXT: entry: // CHECK-MTE-BTI-NEXT: ret i32 1 // // // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_inline1._Msve2-aesMwfxt -// CHECK-MTE-BTI-SAME: () #[[ATTR14:[0-9]+]] { +// CHECK-MTE-BTI-SAME: () #[[ATTR16:[0-9]+]] { // CHECK-MTE-BTI-NEXT: entry: // CHECK-MTE-BTI-NEXT: ret i32 1 // // // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone -// CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_inline1.default -// CHECK-MTE-BTI-SAME: () #[[ATTR9]] { -// CHECK-MTE-BTI-NEXT: entry: -// CHECK-MTE-BTI-NEXT: ret i32 1 -// -// -// CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_inline1.resolver() comdat { -// CHECK-MTE-BTI-NEXT: resolver_entry: -// CHECK-MTE-BTI-NEXT: call void @__init_cpu_features_resolver() -// CHECK-MTE-BTI-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-MTE-BTI-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 18014743180706560 -// CHECK-MTE-BTI-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 18014743180706560 -// CHECK-MTE-BTI-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] -// CHECK-MTE-BTI-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] -// CHECK-MTE-BTI: resolver_return: -// CHECK-MTE-BTI-NEXT: ret ptr @ftc_inline1._Msve2-aesMwfxt -// CHECK-MTE-BTI: resolver_else: -// CHECK-MTE-BTI-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-MTE-BTI-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 4194304 -// CHECK-MTE-BTI-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 4194304 -// CHECK-MTE-BTI-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] -// CHECK-MTE-BTI-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] -// CHECK-MTE-BTI: resolver_return1: -// CHECK-MTE-BTI-NEXT: ret ptr @ftc_inline1._Mrcpc -// CHECK-MTE-BTI: resolver_else2: -// CHECK-MTE-BTI-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-MTE-BTI-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 769 -// CHECK-MTE-BTI-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 769 -// CHECK-MTE-BTI-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]] -// CHECK-MTE-BTI-NEXT: br i1 [[TMP11]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]] -// CHECK-MTE-BTI: resolver_return3: -// CHECK-MTE-BTI-NEXT: ret ptr @ftc_inline1._MrngMsimd -// CHECK-MTE-BTI: resolver_else4: -// CHECK-MTE-BTI-NEXT: ret ptr @ftc_inline1.default -// -// -// CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_inline3._Mbti -// CHECK-MTE-BTI-SAME: () #[[ATTR7]] { +// CHECK-MTE-BTI-SAME: () #[[ATTR8]] { // CHECK-MTE-BTI-NEXT: entry: // CHECK-MTE-BTI-NEXT: ret i32 3 // // // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_inline3._MsbMsve -// CHECK-MTE-BTI-SAME: () #[[ATTR15:[0-9]+]] { +// CHECK-MTE-BTI-SAME: () #[[ATTR17:[0-9]+]] { // CHECK-MTE-BTI-NEXT: entry: // CHECK-MTE-BTI-NEXT: ret i32 3 // // // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_inline3.default -// CHECK-MTE-BTI-SAME: () #[[ATTR9]] { +// CHECK-MTE-BTI-SAME: () #[[ATTR4]] { // CHECK-MTE-BTI-NEXT: entry: // CHECK-MTE-BTI-NEXT: ret i32 3 // diff --git a/clang/test/CodeGen/attr-target-version-riscv.c b/clang/test/CodeGen/attr-target-version-riscv.c index 3eff52a7c7710..fbead04caf455 100644 --- a/clang/test/CodeGen/attr-target-version-riscv.c +++ b/clang/test/CodeGen/attr-target-version-riscv.c @@ -49,163 +49,6 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5() + foo6() + foo7(); // CHECK-NEXT: ret i32 1 // // -// CHECK-LABEL: define dso_local signext i32 @foo1.default( -// CHECK-SAME: ) #[[ATTR1:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local signext i32 @foo2._zbb( -// CHECK-SAME: ) #[[ATTR2:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local signext i32 @foo2._m( -// CHECK-SAME: ) #[[ATTR3:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local signext i32 @foo2.default( -// CHECK-SAME: ) #[[ATTR1]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local signext i32 @foo3._c_zbb( -// CHECK-SAME: ) #[[ATTR4:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local signext i32 @foo3._m( -// CHECK-SAME: ) #[[ATTR3]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local signext i32 @foo3.default( -// CHECK-SAME: ) #[[ATTR1]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local signext i32 @foo4._zba( -// CHECK-SAME: ) #[[ATTR5:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local signext i32 @foo4._zbb( -// CHECK-SAME: ) #[[ATTR2]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local signext i32 @foo4._zba_zbb( -// CHECK-SAME: ) #[[ATTR6:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local signext i32 @foo4.default( -// CHECK-SAME: ) #[[ATTR1]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local signext i32 @foo5._zba( -// CHECK-SAME: ) #[[ATTR5]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local signext i32 @foo5._zba_zbb( -// CHECK-SAME: ) #[[ATTR6]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local signext i32 @foo5._zbb( -// CHECK-SAME: ) #[[ATTR2]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local signext i32 @foo5.default( -// CHECK-SAME: ) #[[ATTR1]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local signext i32 @foo6._zba( -// CHECK-SAME: ) #[[ATTR5]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local signext i32 @foo6._zbb( -// CHECK-SAME: ) #[[ATTR2]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local signext i32 @foo6._zba_zbb( -// CHECK-SAME: ) #[[ATTR6]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local signext i32 @foo6.default( -// CHECK-SAME: ) #[[ATTR1]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local signext i32 @foo7._zba( -// CHECK-SAME: ) #[[ATTR5]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local signext i32 @foo7._zbb( -// CHECK-SAME: ) #[[ATTR2]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local signext i32 @foo7._zba_zbb( -// CHECK-SAME: ) #[[ATTR6]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local signext i32 @foo7.default( -// CHECK-SAME: ) #[[ATTR1]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local signext i32 @bar( -// CHECK-SAME: ) #[[ATTR1]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[CALL:%.*]] = call signext i32 @foo1() -// CHECK-NEXT: [[CALL1:%.*]] = call signext i32 @foo2() -// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]] -// CHECK-NEXT: [[CALL2:%.*]] = call signext i32 @foo3() -// CHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]] -// CHECK-NEXT: [[CALL4:%.*]] = call signext i32 @foo4() -// CHECK-NEXT: [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CALL4]] -// CHECK-NEXT: [[CALL6:%.*]] = call signext i32 @foo5() -// CHECK-NEXT: [[ADD7:%.*]] = add nsw i32 [[ADD5]], [[CALL6]] -// CHECK-NEXT: [[CALL8:%.*]] = call signext i32 @foo6() -// CHECK-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD7]], [[CALL8]] -// CHECK-NEXT: [[CALL10:%.*]] = call signext i32 @foo7() -// CHECK-NEXT: [[ADD11:%.*]] = add nsw i32 [[ADD9]], [[CALL10]] -// CHECK-NEXT: ret i32 [[ADD11]] -// -// // CHECK-LABEL: define weak_odr ptr @foo1.resolver() comdat { // CHECK-NEXT: resolver_entry: // CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null) @@ -219,6 +62,18 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5() + foo6() + foo7(); // CHECK-NEXT: ret ptr @foo1.default // // +// CHECK-LABEL: define dso_local signext i32 @foo1.default( +// CHECK-SAME: ) #[[ATTR1:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// +// CHECK-LABEL: define dso_local signext i32 @foo2._zbb( +// CHECK-SAME: ) #[[ATTR2:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// // CHECK-LABEL: define weak_odr ptr @foo2.resolver() comdat { // CHECK-NEXT: resolver_entry: // CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null) @@ -239,6 +94,24 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5() + foo6() + foo7(); // CHECK-NEXT: ret ptr @foo2.default // // +// CHECK-LABEL: define dso_local signext i32 @foo2._m( +// CHECK-SAME: ) #[[ATTR3:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// +// CHECK-LABEL: define dso_local signext i32 @foo2.default( +// CHECK-SAME: ) #[[ATTR1]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// +// CHECK-LABEL: define dso_local signext i32 @foo3._c_zbb( +// CHECK-SAME: ) #[[ATTR4:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// // CHECK-LABEL: define weak_odr ptr @foo3.resolver() comdat { // CHECK-NEXT: resolver_entry: // CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null) @@ -259,6 +132,24 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5() + foo6() + foo7(); // CHECK-NEXT: ret ptr @foo3.default // // +// CHECK-LABEL: define dso_local signext i32 @foo3._m( +// CHECK-SAME: ) #[[ATTR3]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// +// CHECK-LABEL: define dso_local signext i32 @foo3.default( +// CHECK-SAME: ) #[[ATTR1]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// +// CHECK-LABEL: define dso_local signext i32 @foo4._zba( +// CHECK-SAME: ) #[[ATTR5:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// // CHECK-LABEL: define weak_odr ptr @foo4.resolver() comdat { // CHECK-NEXT: resolver_entry: // CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null) @@ -286,6 +177,30 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5() + foo6() + foo7(); // CHECK-NEXT: ret ptr @foo4.default // // +// CHECK-LABEL: define dso_local signext i32 @foo4._zbb( +// CHECK-SAME: ) #[[ATTR2]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// +// CHECK-LABEL: define dso_local signext i32 @foo4._zba_zbb( +// CHECK-SAME: ) #[[ATTR6:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// +// CHECK-LABEL: define dso_local signext i32 @foo4.default( +// CHECK-SAME: ) #[[ATTR1]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// +// CHECK-LABEL: define dso_local signext i32 @foo5._zba( +// CHECK-SAME: ) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// // CHECK-LABEL: define weak_odr ptr @foo5.resolver() comdat { // CHECK-NEXT: resolver_entry: // CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null) @@ -313,6 +228,30 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5() + foo6() + foo7(); // CHECK-NEXT: ret ptr @foo5.default // // +// CHECK-LABEL: define dso_local signext i32 @foo5._zba_zbb( +// CHECK-SAME: ) #[[ATTR6]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// +// CHECK-LABEL: define dso_local signext i32 @foo5._zbb( +// CHECK-SAME: ) #[[ATTR2]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// +// CHECK-LABEL: define dso_local signext i32 @foo5.default( +// CHECK-SAME: ) #[[ATTR1]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// +// CHECK-LABEL: define dso_local signext i32 @foo6._zba( +// CHECK-SAME: ) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// // CHECK-LABEL: define weak_odr ptr @foo6.resolver() comdat { // CHECK-NEXT: resolver_entry: // CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null) @@ -340,6 +279,30 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5() + foo6() + foo7(); // CHECK-NEXT: ret ptr @foo6.default // // +// CHECK-LABEL: define dso_local signext i32 @foo6._zbb( +// CHECK-SAME: ) #[[ATTR2]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// +// CHECK-LABEL: define dso_local signext i32 @foo6._zba_zbb( +// CHECK-SAME: ) #[[ATTR6]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// +// CHECK-LABEL: define dso_local signext i32 @foo6.default( +// CHECK-SAME: ) #[[ATTR1]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// +// CHECK-LABEL: define dso_local signext i32 @foo7._zba( +// CHECK-SAME: ) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// // CHECK-LABEL: define weak_odr ptr @foo7.resolver() comdat { // CHECK-NEXT: resolver_entry: // CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null) @@ -366,6 +329,43 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5() + foo6() + foo7(); // CHECK: resolver_else4: // CHECK-NEXT: ret ptr @foo7.default // +// +// CHECK-LABEL: define dso_local signext i32 @foo7._zbb( +// CHECK-SAME: ) #[[ATTR2]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// +// CHECK-LABEL: define dso_local signext i32 @foo7._zba_zbb( +// CHECK-SAME: ) #[[ATTR6]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// +// CHECK-LABEL: define dso_local signext i32 @foo7.default( +// CHECK-SAME: ) #[[ATTR1]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// +// CHECK-LABEL: define dso_local signext i32 @bar( +// CHECK-SAME: ) #[[ATTR1]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[CALL:%.*]] = call signext i32 @foo1() +// CHECK-NEXT: [[CALL1:%.*]] = call signext i32 @foo2() +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]] +// CHECK-NEXT: [[CALL2:%.*]] = call signext i32 @foo3() +// CHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]] +// CHECK-NEXT: [[CALL4:%.*]] = call signext i32 @foo4() +// CHECK-NEXT: [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CALL4]] +// CHECK-NEXT: [[CALL6:%.*]] = call signext i32 @foo5() +// CHECK-NEXT: [[ADD7:%.*]] = add nsw i32 [[ADD5]], [[CALL6]] +// CHECK-NEXT: [[CALL8:%.*]] = call signext i32 @foo6() +// CHECK-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD7]], [[CALL8]] +// CHECK-NEXT: [[CALL10:%.*]] = call signext i32 @foo7() +// CHECK-NEXT: [[ADD11:%.*]] = add nsw i32 [[ADD9]], [[CALL10]] +// CHECK-NEXT: ret i32 [[ADD11]] +// //. // CHECK: attributes #[[ATTR0]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } // CHECK: attributes #[[ATTR1]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i" } diff --git a/clang/test/CodeGenCXX/attr-target-clones-aarch64.cpp b/clang/test/CodeGenCXX/attr-target-clones-aarch64.cpp index 4f553262c73b5..a502d24f17880 100644 --- a/clang/test/CodeGenCXX/attr-target-clones-aarch64.cpp +++ b/clang/test/CodeGenCXX/attr-target-clones-aarch64.cpp @@ -9,7 +9,7 @@ int bar() { } template struct MyClass { - int __attribute__((target_clones("frintts", "ssbs+sme-f64f64"))) foo_tml() { return 1; } + int __attribute__((target_clones("frintts", "ssbs+sme-f64f64", "default"))) foo_tml() { return 1; } }; template struct MyClass { @@ -41,9 +41,7 @@ void run_foo_tml() { //. // CHECK: @__aarch64_cpu_features = external dso_local global { i64 } // CHECK: @_Z7foo_ovli = weak_odr ifunc i32 (i32), ptr @_Z7foo_ovli.resolver -// CHECK: @_Z7foo_ovlv = weak_odr ifunc i32 (), ptr @_Z7foo_ovlv.resolver // CHECK: @_ZN7MyClassIssE7foo_tmlEv = weak_odr ifunc i32 (ptr), ptr @_ZN7MyClassIssE7foo_tmlEv.resolver -// CHECK: @_ZN7MyClassIisE7foo_tmlEv = weak_odr ifunc i32 (ptr), ptr @_ZN7MyClassIisE7foo_tmlEv.resolver //. // CHECK-LABEL: define dso_local noundef i32 @_Z7foo_ovli._Mfp16( // CHECK-SAME: i32 noundef [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] { @@ -53,18 +51,12 @@ void run_foo_tml() { // CHECK-NEXT: ret i32 1 // // -// CHECK-LABEL: define weak_odr ptr @_Z7foo_ovli.resolver() comdat { -// CHECK-NEXT: [[RESOLVER_ENTRY:.*:]] -// CHECK-NEXT: call void @__init_cpu_features_resolver() -// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 65792 -// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 65792 -// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] -// CHECK-NEXT: br i1 [[TMP3]], label %[[RESOLVER_RETURN:.*]], label %[[RESOLVER_ELSE:.*]] -// CHECK: [[RESOLVER_RETURN]]: -// CHECK-NEXT: ret ptr @_Z7foo_ovli._Mfp16 -// CHECK: [[RESOLVER_ELSE]]: -// CHECK-NEXT: ret ptr @_Z7foo_ovli.default +// CHECK-LABEL: define dso_local noundef i32 @_Z7foo_ovli.default( +// CHECK-SAME: i32 noundef [[TMP0:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK-NEXT: ret i32 1 // // // CHECK-LABEL: define dso_local noundef i32 @_Z7foo_ovlv._Mfp16( @@ -73,22 +65,8 @@ void run_foo_tml() { // CHECK-NEXT: ret i32 2 // // -// CHECK-LABEL: define weak_odr ptr @_Z7foo_ovlv.resolver() comdat { -// CHECK-NEXT: [[RESOLVER_ENTRY:.*:]] -// CHECK-NEXT: call void @__init_cpu_features_resolver() -// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 65792 -// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 65792 -// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] -// CHECK-NEXT: br i1 [[TMP3]], label %[[RESOLVER_RETURN:.*]], label %[[RESOLVER_ELSE:.*]] -// CHECK: [[RESOLVER_RETURN]]: -// CHECK-NEXT: ret ptr @_Z7foo_ovlv._Mfp16 -// CHECK: [[RESOLVER_ELSE]]: -// CHECK-NEXT: ret ptr @_Z7foo_ovlv.default -// -// // CHECK-LABEL: define dso_local noundef i32 @_Z3barv( -// CHECK-SAME: ) #[[ATTR1:[0-9]+]] { +// CHECK-SAME: ) #[[ATTR2:[0-9]+]] { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[CALL:%.*]] = call noundef i32 @_Z7foo_ovli(i32 noundef 1) // CHECK-NEXT: [[CALL1:%.*]] = call noundef i32 @_Z7foo_ovlv() @@ -97,7 +75,7 @@ void run_foo_tml() { // // // CHECK-LABEL: define dso_local void @_Z11run_foo_tmlv( -// CHECK-SAME: ) #[[ATTR1]] { +// CHECK-SAME: ) #[[ATTR2]] { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[MC1:%.*]] = alloca [[STRUCT_MYCLASS:%.*]], align 1 // CHECK-NEXT: [[MC2:%.*]] = alloca [[STRUCT_MYCLASS_0:%.*]], align 1 @@ -111,7 +89,7 @@ void run_foo_tml() { // // // CHECK-LABEL: define linkonce_odr noundef i32 @_ZN7MyClassIfsE7foo_tmlEv( -// CHECK-SAME: ptr noundef nonnull align 1 dereferenceable(1) [[THIS:%.*]]) #[[ATTR1]] comdat { +// CHECK-SAME: ptr noundef nonnull align 1 dereferenceable(1) [[THIS:%.*]]) #[[ATTR2]] comdat { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -120,7 +98,7 @@ void run_foo_tml() { // // // CHECK-LABEL: define linkonce_odr noundef i32 @_ZN7MyClassIdfE7foo_tmlEv( -// CHECK-SAME: ptr noundef nonnull align 1 dereferenceable(1) [[THIS:%.*]]) #[[ATTR1]] comdat { +// CHECK-SAME: ptr noundef nonnull align 1 dereferenceable(1) [[THIS:%.*]]) #[[ATTR2]] comdat { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -128,22 +106,22 @@ void run_foo_tml() { // CHECK-NEXT: ret i32 4 // // -// CHECK-LABEL: define dso_local noundef i32 @_Z7foo_ovli.default( -// CHECK-SAME: i32 noundef [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local noundef i32 @_Z7foo_ovlv.default( -// CHECK-SAME: ) #[[ATTR2]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: ret i32 2 +// CHECK-LABEL: define weak_odr ptr @_Z7foo_ovli.resolver() comdat { +// CHECK-NEXT: [[RESOLVER_ENTRY:.*:]] +// CHECK-NEXT: call void @__init_cpu_features_resolver() +// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 65792 +// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 65792 +// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] +// CHECK-NEXT: br i1 [[TMP3]], label %[[RESOLVER_RETURN:.*]], label %[[RESOLVER_ELSE:.*]] +// CHECK: [[RESOLVER_RETURN]]: +// CHECK-NEXT: ret ptr @_Z7foo_ovli._Mfp16 +// CHECK: [[RESOLVER_ELSE]]: +// CHECK-NEXT: ret ptr @_Z7foo_ovli.default // // // CHECK-LABEL: define linkonce_odr noundef i32 @_ZN7MyClassIssE7foo_tmlEv._Mfrintts( -// CHECK-SAME: ptr noundef nonnull align 1 dereferenceable(1) [[THIS:%.*]]) #[[ATTR3:[0-9]+]] comdat { +// CHECK-SAME: ptr noundef nonnull align 1 dereferenceable(1) [[THIS:%.*]]) #[[ATTR5:[0-9]+]] comdat { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -152,7 +130,7 @@ void run_foo_tml() { // // // CHECK-LABEL: define linkonce_odr noundef i32 @_ZN7MyClassIssE7foo_tmlEv._Msme-f64f64Mssbs( -// CHECK-SAME: ptr noundef nonnull align 1 dereferenceable(1) [[THIS:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK-SAME: ptr noundef nonnull align 1 dereferenceable(1) [[THIS:%.*]]) #[[ATTR6:[0-9]+]] comdat { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -161,7 +139,7 @@ void run_foo_tml() { // // // CHECK-LABEL: define linkonce_odr noundef i32 @_ZN7MyClassIssE7foo_tmlEv.default( -// CHECK-SAME: ptr noundef nonnull align 1 dereferenceable(1) [[THIS:%.*]]) #[[ATTR2]] comdat { +// CHECK-SAME: ptr noundef nonnull align 1 dereferenceable(1) [[THIS:%.*]]) #[[ATTR1]] comdat { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -192,7 +170,7 @@ void run_foo_tml() { // // // CHECK-LABEL: define linkonce_odr noundef i32 @_ZN7MyClassIisE7foo_tmlEv._Mfrintts( -// CHECK-SAME: ptr noundef nonnull align 1 dereferenceable(1) [[THIS:%.*]]) #[[ATTR3]] comdat { +// CHECK-SAME: ptr noundef nonnull align 1 dereferenceable(1) [[THIS:%.*]]) #[[ATTR5]] comdat { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -201,44 +179,13 @@ void run_foo_tml() { // // // CHECK-LABEL: define linkonce_odr noundef i32 @_ZN7MyClassIisE7foo_tmlEv._Msme-f64f64Mssbs( -// CHECK-SAME: ptr noundef nonnull align 1 dereferenceable(1) [[THIS:%.*]]) #[[ATTR4]] comdat { +// CHECK-SAME: ptr noundef nonnull align 1 dereferenceable(1) [[THIS:%.*]]) #[[ATTR6]] comdat { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: ret i32 2 // -// -// CHECK-LABEL: define linkonce_odr noundef i32 @_ZN7MyClassIisE7foo_tmlEv.default( -// CHECK-SAME: ptr noundef nonnull align 1 dereferenceable(1) [[THIS:%.*]]) #[[ATTR2]] comdat { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 -// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-NEXT: ret i32 2 -// -// -// CHECK-LABEL: define weak_odr ptr @_ZN7MyClassIisE7foo_tmlEv.resolver() comdat { -// CHECK-NEXT: [[RESOLVER_ENTRY:.*:]] -// CHECK-NEXT: call void @__init_cpu_features_resolver() -// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 36596145153180416 -// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 36596145153180416 -// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] -// CHECK-NEXT: br i1 [[TMP3]], label %[[RESOLVER_RETURN:.*]], label %[[RESOLVER_ELSE:.*]] -// CHECK: [[RESOLVER_RETURN]]: -// CHECK-NEXT: ret ptr @_ZN7MyClassIisE7foo_tmlEv._Msme-f64f64Mssbs -// CHECK: [[RESOLVER_ELSE]]: -// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 16777472 -// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 16777472 -// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] -// CHECK-NEXT: br i1 [[TMP7]], label %[[RESOLVER_RETURN1:.*]], label %[[RESOLVER_ELSE2:.*]] -// CHECK: [[RESOLVER_RETURN1]]: -// CHECK-NEXT: ret ptr @_ZN7MyClassIisE7foo_tmlEv._Mfrintts -// CHECK: [[RESOLVER_ELSE2]]: -// CHECK-NEXT: ret ptr @_ZN7MyClassIisE7foo_tmlEv.default -// //. // CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4} // CHECK: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"} diff --git a/clang/test/CodeGenCXX/attr-target-version-riscv.cpp b/clang/test/CodeGenCXX/attr-target-version-riscv.cpp index 827cd1ef9750c..ffb4576b3cd30 100644 --- a/clang/test/CodeGenCXX/attr-target-version-riscv.cpp +++ b/clang/test/CodeGenCXX/attr-target-version-riscv.cpp @@ -49,155 +49,6 @@ int bar() { return foo1() + foo2() + foo3(); } // CHECK-NEXT: ret i32 1 // // -// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo1v.default( -// CHECK-SAME: ) #[[ATTR1:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo2v._zbb( -// CHECK-SAME: ) #[[ATTR2:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo2v._m( -// CHECK-SAME: ) #[[ATTR1]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo2v.default( -// CHECK-SAME: ) #[[ATTR1]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo3v._c_zbb( -// CHECK-SAME: ) #[[ATTR3:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo3v._m( -// CHECK-SAME: ) #[[ATTR1]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo3v.default( -// CHECK-SAME: ) #[[ATTR1]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo4v._zba( -// CHECK-SAME: ) #[[ATTR4:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo4v._zbb( -// CHECK-SAME: ) #[[ATTR2]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo4v._zba_zbb( -// CHECK-SAME: ) #[[ATTR5:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo4v.default( -// CHECK-SAME: ) #[[ATTR1]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo5v._zba( -// CHECK-SAME: ) #[[ATTR4]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo5v._zba_zbb( -// CHECK-SAME: ) #[[ATTR5]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo5v._zbb( -// CHECK-SAME: ) #[[ATTR2]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo5v.default( -// CHECK-SAME: ) #[[ATTR1]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo6v._zba( -// CHECK-SAME: ) #[[ATTR4]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo6v._zbb( -// CHECK-SAME: ) #[[ATTR2]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo6v._zba_zbb( -// CHECK-SAME: ) #[[ATTR5]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo6v.default( -// CHECK-SAME: ) #[[ATTR1]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo7v._zba( -// CHECK-SAME: ) #[[ATTR4]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo7v._zbb( -// CHECK-SAME: ) #[[ATTR2]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo7v._zba_zbb( -// CHECK-SAME: ) #[[ATTR5]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo7v.default( -// CHECK-SAME: ) #[[ATTR1]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define dso_local noundef signext i32 @_Z3barv( -// CHECK-SAME: ) #[[ATTR1]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z4foo1v() -// CHECK-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_Z4foo2v() -// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]] -// CHECK-NEXT: [[CALL2:%.*]] = call noundef signext i32 @_Z4foo3v() -// CHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]] -// CHECK-NEXT: ret i32 [[ADD3]] -// -// // CHECK-LABEL: define weak_odr ptr @_Z4foo1v.resolver() comdat { // CHECK-NEXT: resolver_entry: // CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null) @@ -211,6 +62,18 @@ int bar() { return foo1() + foo2() + foo3(); } // CHECK-NEXT: ret ptr @_Z4foo1v.default // // +// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo1v.default( +// CHECK-SAME: ) #[[ATTR1:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// +// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo2v._zbb( +// CHECK-SAME: ) #[[ATTR2:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// // CHECK-LABEL: define weak_odr ptr @_Z4foo2v.resolver() comdat { // CHECK-NEXT: resolver_entry: // CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null) @@ -231,6 +94,24 @@ int bar() { return foo1() + foo2() + foo3(); } // CHECK-NEXT: ret ptr @_Z4foo2v.default // // +// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo2v._m( +// CHECK-SAME: ) #[[ATTR1]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// +// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo2v.default( +// CHECK-SAME: ) #[[ATTR1]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// +// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo3v._c_zbb( +// CHECK-SAME: ) #[[ATTR3:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// // CHECK-LABEL: define weak_odr ptr @_Z4foo3v.resolver() comdat { // CHECK-NEXT: resolver_entry: // CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null) @@ -251,6 +132,24 @@ int bar() { return foo1() + foo2() + foo3(); } // CHECK-NEXT: ret ptr @_Z4foo3v.default // // +// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo3v._m( +// CHECK-SAME: ) #[[ATTR1]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// +// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo3v.default( +// CHECK-SAME: ) #[[ATTR1]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// +// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo4v._zba( +// CHECK-SAME: ) #[[ATTR4:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// // CHECK-LABEL: define weak_odr ptr @_Z4foo4v.resolver() comdat { // CHECK-NEXT: resolver_entry: // CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null) @@ -278,6 +177,30 @@ int bar() { return foo1() + foo2() + foo3(); } // CHECK-NEXT: ret ptr @_Z4foo4v.default // // +// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo4v._zbb( +// CHECK-SAME: ) #[[ATTR2]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// +// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo4v._zba_zbb( +// CHECK-SAME: ) #[[ATTR5:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// +// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo4v.default( +// CHECK-SAME: ) #[[ATTR1]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// +// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo5v._zba( +// CHECK-SAME: ) #[[ATTR4]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// // CHECK-LABEL: define weak_odr ptr @_Z4foo5v.resolver() comdat { // CHECK-NEXT: resolver_entry: // CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null) @@ -305,6 +228,30 @@ int bar() { return foo1() + foo2() + foo3(); } // CHECK-NEXT: ret ptr @_Z4foo5v.default // // +// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo5v._zba_zbb( +// CHECK-SAME: ) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// +// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo5v._zbb( +// CHECK-SAME: ) #[[ATTR2]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// +// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo5v.default( +// CHECK-SAME: ) #[[ATTR1]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// +// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo6v._zba( +// CHECK-SAME: ) #[[ATTR4]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// // CHECK-LABEL: define weak_odr ptr @_Z4foo6v.resolver() comdat { // CHECK-NEXT: resolver_entry: // CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null) @@ -332,6 +279,30 @@ int bar() { return foo1() + foo2() + foo3(); } // CHECK-NEXT: ret ptr @_Z4foo6v.default // // +// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo6v._zbb( +// CHECK-SAME: ) #[[ATTR2]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// +// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo6v._zba_zbb( +// CHECK-SAME: ) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// +// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo6v.default( +// CHECK-SAME: ) #[[ATTR1]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// +// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo7v._zba( +// CHECK-SAME: ) #[[ATTR4]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// // CHECK-LABEL: define weak_odr ptr @_Z4foo7v.resolver() comdat { // CHECK-NEXT: resolver_entry: // CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null) @@ -358,6 +329,35 @@ int bar() { return foo1() + foo2() + foo3(); } // CHECK: resolver_else4: // CHECK-NEXT: ret ptr @_Z4foo7v.default // +// +// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo7v._zbb( +// CHECK-SAME: ) #[[ATTR2]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// +// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo7v._zba_zbb( +// CHECK-SAME: ) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// +// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo7v.default( +// CHECK-SAME: ) #[[ATTR1]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 1 +// +// +// CHECK-LABEL: define dso_local noundef signext i32 @_Z3barv( +// CHECK-SAME: ) #[[ATTR1]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z4foo1v() +// CHECK-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_Z4foo2v() +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]] +// CHECK-NEXT: [[CALL2:%.*]] = call noundef signext i32 @_Z4foo3v() +// CHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]] +// CHECK-NEXT: ret i32 [[ADD3]] +// //. // CHECK: attributes #[[ATTR0]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+m,+v,+zicsr,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } // CHECK: attributes #[[ATTR1]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zmmul" } diff --git a/clang/test/Sema/attr-target-clones-aarch64.c b/clang/test/Sema/attr-target-clones-aarch64.c index 784646ed15d20..93d87cef54569 100644 --- a/clang/test/Sema/attr-target-clones-aarch64.c +++ b/clang/test/Sema/attr-target-clones-aarch64.c @@ -13,6 +13,8 @@ int redecl(void); int __attribute__((target_clones("frintts", "simd+fp", "default"))) redecl(void) { return 1; } int __attribute__((target_clones("jscvt+fcma", "rcpc", "default"))) redecl2(void); +// expected-error@+2 {{'target_clones' attribute does not match previous declaration}} +// expected-note@-2 {{previous declaration is here}} int __attribute__((target_clones("jscvt+fcma", "rcpc"))) redecl2(void) { return 1; } int __attribute__((target_clones("sve+dotprod"))) redecl3(void);