diff --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index 71d8d3c0c0771..81cc5d0985476 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -7529,13 +7529,9 @@ vec_pack(vector double __a, vector double __b) {
 #ifdef __POWER9_VECTOR__
 static __inline__ vector unsigned short __ATTRS_o_ai
 vec_pack_to_short_fp32(vector float __a, vector float __b) {
-  vector float __resa = __builtin_vsx_xvcvsphp(__a);
-  vector float __resb = __builtin_vsx_xvcvsphp(__b);
-#ifdef __LITTLE_ENDIAN__
-  return (vector unsigned short)vec_mergee(__resa, __resb);
-#else
-  return (vector unsigned short)vec_mergeo(__resa, __resb);
-#endif
+  vector unsigned int __resa = (vector unsigned int)__builtin_vsx_xvcvsphp(__a);
+  vector unsigned int __resb = (vector unsigned int)__builtin_vsx_xvcvsphp(__b);
+  return vec_pack(__resa, __resb);
 }
 
 #endif
diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-p9vector.c b/clang/test/CodeGen/PowerPC/builtins-ppc-p9vector.c
index 68d32ee14c8fa..824267b98564e 100644
--- a/clang/test/CodeGen/PowerPC/builtins-ppc-p9vector.c
+++ b/clang/test/CodeGen/PowerPC/builtins-ppc-p9vector.c
@@ -854,15 +854,13 @@ vector unsigned short test74(void) {
 // CHECK-BE: @llvm.ppc.vsx.xvcvsphp(<4 x float>
 // CHECK-BE: @llvm.ppc.vsx.xvcvsphp(<4 x float>
 // CHECK-BE: [[REG0:%[0-9]+]] = call <4 x i32> @llvm.ppc.altivec.vperm
-// CHECK-BE-NEXT: [[REG1:%[0-9]+]] = bitcast <4 x i32> [[REG0]] to <4 x float>
-// CHECK-BE-NEXT: [[REG2:%[0-9]+]] = bitcast <4 x float> [[REG1]] to <8 x i16>
-// CHECK-BE-NEXT: ret <8 x i16> [[REG2]]
+// CHECK-BE-NEXT: [[REG1:%[0-9]+]] = bitcast <4 x i32> [[REG0]] to <8 x i16>
+// CHECK-BE-NEXT: ret <8 x i16> [[REG1]]
 // CHECK: @llvm.ppc.vsx.xvcvsphp(<4 x float>
 // CHECK: @llvm.ppc.vsx.xvcvsphp(<4 x float>
 // CHECK: [[REG0:%[0-9]+]] = call <4 x i32> @llvm.ppc.altivec.vperm
-// CHECK-NEXT: [[REG1:%[0-9]+]] = bitcast <4 x i32> [[REG0]] to <4 x float>
-// CHECK-NEXT: [[REG2:%[0-9]+]] = bitcast <4 x float> [[REG1]] to <8 x i16>
-// CHECK-NEXT: ret <8 x i16> [[REG2]]
+// CHECK-NEXT: [[REG1:%[0-9]+]] = bitcast <4 x i32> [[REG0]] to <8 x i16>
+// CHECK-NEXT: ret <8 x i16> [[REG1]]
   return vec_pack_to_short_fp32(vfa, vfb);
 }
 vector unsigned int test75(void) {