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[X86][GISel] Add legalization support for non-constant G_BUILD_VECTOR
backend:X86
llvm:globalisel
#143099
opened Jun 6, 2025 by
RKSimon
[TableGen] Move getSuperRegForSubReg into CodeGenRegBank. NFC.
llvm:globalisel
tablegen
#142979
opened Jun 5, 2025 by
jayfoad
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[AArch64][GlobalISel] Expand 64bit extracts to 128bit to allow more patterns
backend:AArch64
llvm:globalisel
#142904
opened Jun 5, 2025 by
davemgreen
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AMDGPU/GlobalISel: Add waterfall lowering in regbanklegalize
backend:AMDGPU
llvm:globalisel
#142790
opened Jun 4, 2025 by
petar-avramovic
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AMDGPU/GlobalISel: Improve readanylane combines in regbanklegalize
backend:AMDGPU
llvm:globalisel
#142789
opened Jun 4, 2025 by
petar-avramovic
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AMDGPU/GlobalISel: Add tests for missing readanylane combines
backend:AMDGPU
llvm:globalisel
#142788
opened Jun 4, 2025 by
petar-avramovic
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[AArch64][GlobalISel] Prefer DUPLANE to REV
backend:AArch64
llvm:globalisel
#142725
opened Jun 4, 2025 by
davemgreen
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[AMDGPU] Add DAG mutation to improve scheduling before barriers
backend:AMDGPU
llvm:globalisel
#142716
opened Jun 4, 2025 by
perlfu
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[AMDGPU] New RegBankSelect: Add rules for
G_PTRTOINT and G_INTTOPTR
backend:AMDGPU
llvm:globalisel
#142604
opened Jun 3, 2025 by
Pierre-vh
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[AMDGPU] Improve test coverage for G_INTTOPTR and G_PTRTOINT
backend:AMDGPU
llvm:globalisel
#142603
opened Jun 3, 2025 by
Pierre-vh
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[AMDGPU] New RegBankSelect: Handle all 32/64 bit pointer types for B32/B64 rule
backend:AMDGPU
llvm:globalisel
#142560
opened Jun 3, 2025 by
Pierre-vh
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[X86][GlobalISel] Enable SINCOS with libcall mapping
backend:X86
llvm:globalisel
#142438
opened Jun 2, 2025 by
JaydeepChauhan14
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[AArch64] Use
ZIP1/2 over INS for vector concat
backend:AArch64
llvm:globalisel
#142427
opened Jun 2, 2025 by
Il-Capitano
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[X86] mtune should be generic
backend:X86
debuginfo
llvm:globalisel
#142297
opened May 31, 2025 by
AZero13
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[AMDGPU] Swap select operands to allow later v_cndmask shrinking into vop2
backend:AMDGPU
llvm:globalisel
#142140
opened May 30, 2025 by
mihajlovicana
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[AMDGPU][GlobalISel] Fix G_UNMERGE_VALUES combine
backend:AMDGPU
llvm:globalisel
#141812
opened May 28, 2025 by
mshelego
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[AMDGPU][SDAG] Initial support for ISD::PTRADD
backend:AMDGPU
llvm:globalisel
llvm:SelectionDAG
SelectionDAGISel as well
#141725
opened May 28, 2025 by
ritter-x2a
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[X86][GlobalISel] Support fp80 for G_FPTRUNC and G_FPEXT
backend:X86
llvm:globalisel
#141611
opened May 27, 2025 by
e-kud
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[AMDGPU] Add KnownBits simplification combines to RegBankCombiner
backend:AMDGPU
llvm:globalisel
#141591
opened May 27, 2025 by
Pierre-vh
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[AMDGPU] Add BFX Formation Combines to RegBankCombiner
backend:AMDGPU
llvm:globalisel
#141590
opened May 27, 2025 by
Pierre-vh
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[AMDGPU] Move S_BFE lowering into RegBankCombiner
backend:AMDGPU
llvm:globalisel
#141589
opened May 27, 2025 by
Pierre-vh
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[AMDGPU] Compute GISel KnownBits for S_BFE instructions
backend:AMDGPU
llvm:globalisel
testing-tools
#141588
opened May 27, 2025 by
Pierre-vh
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[AArch64][GlobalISel] Fold buildvector of bitcast
backend:AArch64
llvm:globalisel
#141553
opened May 27, 2025 by
davemgreen
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