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[GlobalISel] support lowering of G_SHUFFLEVECTOR with pointer args
backend:AMDGPU
llvm:globalisel
#141959
opened May 29, 2025 by
stanleygambarin
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[GlobalISel] Add G_CONCAT_VECTOR computeKnownBits
backend:AArch64
llvm:globalisel
#141933
opened May 29, 2025 by
usha1830
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[AMDGPU][GlobalISel] Fix G_UNMERGE_VALUES combine
backend:AMDGPU
llvm:globalisel
#141812
opened May 28, 2025 by
mshelego
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[AMDGPU][SDAG] Initial support for ISD::PTRADD
backend:AMDGPU
llvm:globalisel
llvm:SelectionDAG
SelectionDAGISel as well
#141725
opened May 28, 2025 by
ritter-x2a
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[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible
backend:RISC-V
llvm:globalisel
mc
Machine (object) code
#141663
opened May 27, 2025 by
asb
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[X86][GlobalISel] Support fp80 for G_FPTRUNC and G_FPEXT
backend:X86
llvm:globalisel
#141611
opened May 27, 2025 by
e-kud
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[AMDGPU] Add KnownBits simplification combines to RegBankCombiner
backend:AMDGPU
llvm:globalisel
#141591
opened May 27, 2025 by
Pierre-vh
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[AMDGPU] Add BFX Formation Combines to RegBankCombiner
backend:AMDGPU
llvm:globalisel
#141590
opened May 27, 2025 by
Pierre-vh
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[AMDGPU] Move S_BFE lowering into RegBankCombiner
backend:AMDGPU
llvm:globalisel
#141589
opened May 27, 2025 by
Pierre-vh
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[AMDGPU] Compute GISel KnownBits for S_BFE instructions
backend:AMDGPU
llvm:globalisel
testing-tools
#141588
opened May 27, 2025 by
Pierre-vh
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[AArch64][GlobalISel] Fold buildvector of bitcast
backend:AArch64
llvm:globalisel
#141553
opened May 27, 2025 by
davemgreen
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AMDGPU: Add codegen for atomicrmw operations usub_cond and usub_sat
backend:AMDGPU
llvm:analysis
llvm:globalisel
llvm:ir
llvm:transforms
#141068
opened May 22, 2025 by
anjenner
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[GISel][AArch64] Allow PatLeafs to be imported in GISel which were previously causing warnings
backend:AArch64
llvm:globalisel
llvm:SelectionDAG
SelectionDAGISel as well
tablegen
#140935
opened May 21, 2025 by
jyli0116
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[AMDGPU][MISched] Allow memory ops of different base pointers to be clustered
backend:AMDGPU
llvm:globalisel
#140674
opened May 20, 2025 by
choikwa
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[GlobalISel] Make scalar G_SHUFFLE_VECTOR illegal.
backend:AArch64
backend:AMDGPU
backend:ARM
llvm:globalisel
#140508
opened May 19, 2025 by
davemgreen
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[MCP] Handle iterative simplification during forward copy prop
llvm:globalisel
llvm:regalloc
#140267
opened May 16, 2025 by
preames
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[SPIRV] Add PreLegalizer pattern matching for Headers provided by Clang, e.g. for intrinsics
clang
Clang issues not falling into any other category
HLSL
HLSL Language Support
llvm:globalisel
faceforward
backend:SPIR-V
backend:X86
clang:headers
#139959
opened May 14, 2025 by
kmpeng
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[AMDGPU][GlobalISel] G_UNMERGE_VALUES combining crash
backend:AMDGPU
crash
Prefer [crash-on-valid] or [crash-on-invalid]
llvm:globalisel
#139791
opened May 13, 2025 by
mshelego
[SwitchLowering] Support merging 0 and power-of-2 case.
backend:AArch64
llvm:globalisel
llvm:SelectionDAG
SelectionDAGISel as well
#139736
opened May 13, 2025 by
fhahn
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[GISelValueTracking] Use representation size for G_PTRTOINT src width
backend:AMDGPU
llvm:globalisel
#139608
opened May 12, 2025 by
arichardson
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[IRTranslator] Handle ptrtoaddr
backend:AMDGPU
llvm:globalisel
#139601
opened May 12, 2025 by
arichardson
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[AMDGPU] amdgpu-postlegalizer-combiner incorrectly removes zeroing mask
backend:AMDGPU
llvm:globalisel
#139598
opened May 12, 2025 by
arichardson
[GlobalISel] Add computeNumSignBits for ASHR
backend:AArch64
backend:AMDGPU
llvm:globalisel
#139503
opened May 12, 2025 by
davemgreen
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[IR] Introduce the SelectionDAGISel as well
llvm:transforms
ptrtoaddr instruction
backend:X86
llvm:analysis
llvm:globalisel
llvm:ir
llvm:SandboxIR
llvm:SelectionDAG
#139357
opened May 10, 2025 by
arichardson
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[WIP][AMDGPU][MC] Support 128b rsrc reg in mimg instructions
backend:AMDGPU
llvm:globalisel
mc
Machine (object) code
#139121
opened May 8, 2025 by
jwanggit86
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