-
Notifications
You must be signed in to change notification settings - Fork 13.6k
Issues: llvm/llvm-project
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Author
Label
Projects
Milestones
Assignee
Sort
Issues list
MemoryDependenceAnalysis: Consider a pointer clobbered if it is saved
llvm:analysis
#142096
opened May 30, 2025 by
wzssyqa
Loading…
[RISCV][TTI] Discount slide cost if ri.vinsert/ri.vextract are available
backend:RISC-V
llvm:analysis
#142036
opened May 29, 2025 by
preames
Loading…
AMDGPU: Report special input intrinsics as free
backend:AMDGPU
llvm:analysis
#141948
opened May 29, 2025 by
arsenm
Loading…
AMDGPU: Add baseline cost model tests for special argument intrinsics
backend:AMDGPU
llvm:analysis
#141947
opened May 29, 2025 by
arsenm
Loading…
AMDGPU: Cost model for minimumnum/maximumnum
backend:AMDGPU
llvm:analysis
llvm:transforms
#141946
opened May 29, 2025 by
arsenm
Loading…
AMDGPU: Move fpenvIEEEMode into TTI
backend:AMDGPU
llvm:analysis
#141945
opened May 29, 2025 by
arsenm
Loading…
AMDGPU: Reduce cost of f64 copysign
backend:AMDGPU
llvm:analysis
#141944
opened May 29, 2025 by
arsenm
Loading…
AMDGPU: Fix cost model for 16-bit operations on gfx8
backend:AMDGPU
llvm:analysis
llvm:transforms
#141943
opened May 29, 2025 by
arsenm
Loading…
AMDGPU: Add cost model tests for minimumnum/maximumnum
backend:AMDGPU
llvm:analysis
#141904
opened May 29, 2025 by
arsenm
Loading…
[Analysis] Use the addCost() helper across InlineCost.cpp
llvm:analysis
#141901
opened May 29, 2025 by
arrowd
Loading…
[LV][RFC] Generating conditional VPBB that will be skip when the mask is inactive in VPlan.
backend:RISC-V
llvm:analysis
llvm:transforms
vectorizers
#141900
opened May 29, 2025 by
ElvisWang123
Loading…
[ConstantFolding] Fold sqrt poison -> poison
llvm:analysis
llvm:instcombine
llvm:transforms
#141821
opened May 28, 2025 by
lukel97
Loading…
[LLVM][SCEV] Look through common multiplicand when simplifying compares.
llvm:analysis
llvm:transforms
#141798
opened May 28, 2025 by
paulwalker-arm
Loading…
[NFC][LLVM][LoopVectorize] Change getSmallBestKnownTC to return an ElementCount.
llvm:analysis
llvm:transforms
vectorizers
#141793
opened May 28, 2025 by
paulwalker-arm
Loading…
[LV] Skip sentinel value for FindLastIV reductions when start value is provably less than IV start.
llvm:analysis
llvm:transforms
vectorizers
#141788
opened May 28, 2025 by
Mel-Chen
Loading…
[LV] Extend FindLastIV to unsigned case
llvm:analysis
llvm:transforms
vectorizers
#141752
opened May 28, 2025 by
artagnon
Loading…
[NFC][LLVM] Fix some
llvm namespace usage in Bitcode writer
llvm:analysis
#141709
opened May 28, 2025 by
jurahul
Loading…
[CostModel] Add a DstTy to getShuffleCost
backend:AArch64
backend:AMDGPU
backend:ARM
backend:Hexagon
backend:PowerPC
backend:RISC-V
backend:SystemZ
backend:X86
llvm:analysis
llvm:transforms
vectorizers
#141634
opened May 27, 2025 by
davemgreen
Loading…
"!dbg attachment points at wrong subprogram for function" after InlinerPass
crash
Prefer [crash-on-valid] or [crash-on-invalid]
llvm:analysis
#141568
opened May 27, 2025 by
mikaelholmen
[LoopVectorize] Vectorize the reduction pattern of integer min/max with index. (1/2)
llvm:analysis
llvm:transforms
vectorizers
#141467
opened May 26, 2025 by
Mel-Chen
Loading…
[LV] Vectorize selecting index of min/max element.
llvm:analysis
llvm:transforms
vectorizers
#141431
opened May 25, 2025 by
fhahn
Loading…
[ConstantFolding] Add folding for [de]interleave2, insert and extract
llvm:analysis
llvm:instcombine
llvm:transforms
#141301
opened May 23, 2025 by
npanchen
Loading…
Add constant-folding for unary NVVM intrinsics
backend:NVPTX
llvm:analysis
llvm:instcombine
llvm:ir
llvm:transforms
#141233
opened May 23, 2025 by
LewisCrawford
Loading…
AMDGPU: Add codegen for atomicrmw operations usub_cond and usub_sat
backend:AMDGPU
llvm:analysis
llvm:globalisel
llvm:ir
llvm:transforms
#141068
opened May 22, 2025 by
anjenner
Loading…
[AArch64] Change cost of (s|z)ext <4 x i8> -> <4 x i32> to 2.
backend:AArch64
llvm:analysis
llvm:transforms
#141029
opened May 22, 2025 by
fhahn
Loading…
Previous Next
ProTip!
Adding no:label will show everything without a label.