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Issues list

[MISched] Add templates for creating custom schedulers backend:AArch64 backend:AMDGPU backend:ARM backend:PowerPC backend:RISC-V backend:SystemZ backend:X86 llvm:codegen
#141935 opened May 29, 2025 by wangpc-pp Loading…
8
[llvm] annotate interfaces in AsmParser, BinaryFormat, Bitcode, and Bitstream libraries for DLL export backend:AMDGPU backend:DirectX backend:PowerPC backend:WebAssembly debuginfo llvm:binary-utilities
#141794 opened May 28, 2025 by andrurogerz Loading…
3
[PowerPC10][XXEVAL] Exploit xxeval instruction for cases of the ternary(A,X, and(B,C)), ternary(A,X,B), ternary(A,X,C), ternary(A,X,xor(B,C)) forms. backend:PowerPC
#141733 opened May 28, 2025 by tonykuttai Loading…
4
ppc-reduce-cr-ops mishandles subregister uses and emits verifier error backend:PowerPC crash-on-valid
#141643 opened May 27, 2025 by arsenm
1
[CostModel] Add a DstTy to getShuffleCost backend:AArch64 backend:AMDGPU backend:ARM backend:Hexagon backend:PowerPC backend:RISC-V backend:SystemZ backend:X86 llvm:analysis llvm:transforms vectorizers
#141634 opened May 27, 2025 by davemgreen Loading…
5
Support the inline asm 'a' constraint on PowerPC backend:PowerPC clang:frontend Language frontend issues, e.g. anything involving "Sema" inline-asm
#141604 opened May 27, 2025 by kamaub Loading…
@kamaub
5
[NFC][PowerpC] Add testcases for locking down the xxeval instruction support for ternary operators backend:PowerPC
#141601 opened May 27, 2025 by tonykuttai Loading…
7
[ARM,AArch64] Don't put BTI at asm goto branch targets backend:AArch64 backend:ARM backend:PowerPC backend:X86 clang Clang issues not falling into any other category llvm:ir llvm:SelectionDAG SelectionDAGISel as well
#141562 opened May 27, 2025 by statham-arm Loading…
11
[PowerPC] Spill and restore DMR register backend:PowerPC
#141530 opened May 26, 2025 by lei137 Loading…
2
[VPlan] Use VPInstruction for uniform binops. backend:PowerPC backend:RISC-V llvm:transforms vectorizers
#141429 opened May 25, 2025 by fhahn Loading…
1
[CMake] Move common target dependencies into ${TARGET_LIBRARIES} backend:AArch64 backend:AMDGPU backend:ARC backend:ARM backend:CSKY backend:DirectX backend:Hexagon backend:Lanai backend:loongarch backend:m68k backend:MSP430 backend:NVPTX backend:PowerPC backend:Sparc backend:SPIR-V backend:SystemZ backend:WebAssembly backend:X86
#141271 opened May 23, 2025 by CBSears Loading…
10
Adding Matching and Inference Functionality to Propeller-Patch 1 backend:AArch64 backend:AMDGPU backend:ARM backend:loongarch backend:PowerPC backend:X86 llvm:binary-utilities objectyaml
#140886 opened May 21, 2025 by wdx727 Loading…
14
[NVPTX] Add syncscope support for cmpxchg backend:ARM backend:NVPTX backend:PowerPC backend:RISC-V
#140812 opened May 20, 2025 by akshayrdeodhar Loading…
@akshayrdeodhar
14
[VPlan] Simplify branch on False in VPlan transform (NFC). backend:PowerPC backend:RISC-V llvm:transforms vectorizers
#140409 opened May 17, 2025 by fhahn Loading…
34
[VPlan] Remove ResumePhi opcode, use regular PHI instead (NFC). backend:PowerPC backend:RISC-V llvm:transforms vectorizers
#140405 opened May 17, 2025 by fhahn Loading…
18
[PPC] ROP protection won't be supported with the ELFV1 ABI. backend:PowerPC clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category
#139947 opened May 14, 2025 by mandlebug Loading…
@mandlebug
2
[AIX] PGO codegen changes for function-sections. backend:PowerPC compiler-rt llvm:ir llvm:transforms LTO Link time optimization (regular/full LTO or ThinLTO) PGO Profile Guided Optimizations
#139761 opened May 13, 2025 by mandlebug Loading…
@mandlebug
15
[llvm][TargetLowering] isTruncateFree(Type*, Type*): call isTruncateFree(EVT, EVT) by default backend:ARM backend:Hexagon backend:MSP430 backend:PowerPC backend:SystemZ
#138776 opened May 6, 2025 by justinfargnoli Loading…
@justinfargnoli
8
MachineScheduler: Improve instruction clustering backend:AArch64 backend:AMDGPU backend:PowerPC llvm:codegen llvm:globalisel llvm:transforms
#137784 opened Apr 29, 2025 by ruiling Loading…
23
[PowerPC] frontend get target feature from backend with cpu name backend:PowerPC clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category mc Machine (object) code tablegen
#137670 opened Apr 28, 2025 by diggerlin Loading…
8
[LV] Enable considering higher VFs when data extend ops are present i… backend:AArch64 backend:Hexagon backend:PowerPC backend:WebAssembly llvm:analysis llvm:transforms vectorizers
#137593 opened Apr 28, 2025 by sushgokh Loading…
16
[RFC][TableGen] Require DAG argument for complex operands in InstAlias backend:AArch64 backend:ARM backend:PowerPC tablegen
#136411 opened Apr 19, 2025 by s-barannikov Loading…
9
[LLVM] llvm.fptosi.sat.* and llvm.fptoui.sat.* generate suboptimal code on PowerPC targets backend:PowerPC missed-optimization
#136315 opened Apr 18, 2025 by johnplatts
2
PowerPC/VSX: Select FMINNUM and FMAXNUM backend:PowerPC llvm:SelectionDAG SelectionDAGISel as well
#135739 opened Apr 15, 2025 by wzssyqa • Draft
14
[LV] Move VPlan-based calculateRegisterUsage to VPlanAnalysis (NFC). backend:PowerPC backend:RISC-V llvm:transforms vectorizers
#135673 opened Apr 14, 2025 by fhahn Loading…
4
ProTip! What’s not been updated in a month: updated:<2025-04-30.