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michaelmaitlandmichaelmaitland
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[RISCV][GISEL] instruction-select vmclr (#110782)
This is stacked on #110778. This PR adds and tests renderVLOp too, as that is needed from vmclr.
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‎llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp

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Original file line numberDiff line numberDiff line change
@@ -100,6 +100,8 @@ class RISCVInstructionSelector : public InstructionSelector {
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return selectSHXADD_UWOp(Root, ShAmt);
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}
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ComplexRendererFns renderVLOp(MachineOperand &Root) const;
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// Custom renderers for tablegen
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void renderNegImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
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int OpIdx) const;
@@ -376,6 +378,29 @@ RISCVInstructionSelector::selectSHXADD_UWOp(MachineOperand &Root,
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return std::nullopt;
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}
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InstructionSelector::ComplexRendererFns
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RISCVInstructionSelector::renderVLOp(MachineOperand &Root) const {
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assert(Root.isReg() && "Expected operand to be a Register");
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MachineInstr *RootDef = MRI->getVRegDef(Root.getReg());
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if (RootDef->getOpcode() == TargetOpcode::G_CONSTANT) {
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auto C = RootDef->getOperand(1).getCImm();
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if (C->getValue().isAllOnes())
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// If the operand is a G_CONSTANT with value of all ones it is larger than
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// VLMAX. We convert it to an immediate with value VLMaxSentinel. This is
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// recognized specially by the vsetvli insertion pass.
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return {{[=](MachineInstrBuilder &MIB) {
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MIB.addImm(RISCV::VLMaxSentinel);
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}}};
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if (isUInt<5>(C->getZExtValue())) {
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uint64_t ZExtC = C->getZExtValue();
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return {{[=](MachineInstrBuilder &MIB) { MIB.addImm(ZExtC); }}};
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}
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}
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return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Root.getReg()); }}};
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}
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InstructionSelector::ComplexRendererFns
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RISCVInstructionSelector::selectAddrRegImm(MachineOperand &Root) const {
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if (!Root.isReg())

‎llvm/lib/Target/RISCV/RISCVGISel.td

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@@ -50,6 +50,14 @@ def GIAddrRegImm :
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GIComplexOperandMatcher<s32, "selectAddrRegImm">,
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GIComplexPatternEquiv<AddrRegImm>;
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// FIXME: This is labelled as handling 's32', however the ComplexPattern it
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// refers to handles both i32 and i64 based on the HwMode. Currently this LLT
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// parameter appears to be ignored so this pattern works for both, however we
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// should add a LowLevelTypeByHwMode, and use that to define our XLenLLT instead
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// here.
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def GIVLOp : GIComplexOperandMatcher<s32, "renderVLOp">,
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GIComplexPatternEquiv<VLOp>;
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// Convert from i32 immediate to i64 target immediate to make SelectionDAG type
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// checking happy so we can use ADDIW which expects an XLen immediate.
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def as_i64imm : SDNodeXForm<imm, [{

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop-rv32.mir

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@@ -0,0 +1,76 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc -mtriple=riscv32 -mattr=+v,+m -run-pass=instruction-select \
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# RUN: -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: negative_vl
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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; CHECK-LABEL: name: negative_vl
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; CHECK: [[ADDI:%[0-9]+]]:gprnox0 = ADDI $x0, -2
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; CHECK-NEXT: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 [[ADDI]], 0 /* e8 */
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; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
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; CHECK-NEXT: PseudoRET implicit $v0
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%0:gprb(s32) = G_CONSTANT i32 -2
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%1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
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$v0 = COPY %1(<vscale x 1 x s1>)
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PseudoRET implicit $v0
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...
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---
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name: nonconst_vl
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $x10
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; CHECK-LABEL: name: nonconst_vl
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; CHECK: liveins: $x10
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10
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; CHECK-NEXT: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 [[COPY]], 0 /* e8 */
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; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
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; CHECK-NEXT: PseudoRET implicit $v0
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%0:gprb(s32) = COPY $x10
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%1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
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$v0 = COPY %1(<vscale x 1 x s1>)
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PseudoRET implicit $v0
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...
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---
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name: nonzero_vl
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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; CHECK-LABEL: name: nonzero_vl
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; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 1, 0 /* e8 */
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; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
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; CHECK-NEXT: PseudoRET implicit $v0
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%0:gprb(s32) = G_CONSTANT i32 1
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%1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
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$v0 = COPY %1(<vscale x 1 x s1>)
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PseudoRET implicit $v0
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...
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---
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name: zero_vl
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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; CHECK-LABEL: name: zero_vl
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; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 0, 0 /* e8 */
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; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
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; CHECK-NEXT: PseudoRET implicit $v0
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%0:gprb(s32) = G_CONSTANT i32 0
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%1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
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$v0 = COPY %1(<vscale x 1 x s1>)
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PseudoRET implicit $v0
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...
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‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop-rv64.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc -mtriple=riscv64 -mattr=+v,+m -run-pass=instruction-select \
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# RUN: -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: negative_vl
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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; CHECK-LABEL: name: negative_vl
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; CHECK: [[ADDI:%[0-9]+]]:gprnox0 = ADDI $x0, -2
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; CHECK-NEXT: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 [[ADDI]], 0 /* e8 */
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; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
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; CHECK-NEXT: PseudoRET implicit $v0
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%0:gprb(s64) = G_CONSTANT i64 -2
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%1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s64)
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$v0 = COPY %1(<vscale x 1 x s1>)
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PseudoRET implicit $v0
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...
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---
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name: nonconst_vl
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $x10
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; CHECK-LABEL: name: nonconst_vl
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; CHECK: liveins: $x10
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10
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; CHECK-NEXT: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 [[COPY]], 0 /* e8 */
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; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
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; CHECK-NEXT: PseudoRET implicit $v0
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%0:gprb(s64) = COPY $x10
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%1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s64)
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$v0 = COPY %1(<vscale x 1 x s1>)
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PseudoRET implicit $v0
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...
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---
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name: nonzero_vl
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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; CHECK-LABEL: name: nonzero_vl
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; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 1, 0 /* e8 */
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; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
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; CHECK-NEXT: PseudoRET implicit $v0
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%0:gprb(s64) = G_CONSTANT i64 1
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%1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s64)
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$v0 = COPY %1(<vscale x 1 x s1>)
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PseudoRET implicit $v0
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...
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---
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name: zero_vl
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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; CHECK-LABEL: name: zero_vl
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; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 0, 0 /* e8 */
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; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
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; CHECK-NEXT: PseudoRET implicit $v0
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%0:gprb(s64) = G_CONSTANT i64 0
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%1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s64)
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$v0 = COPY %1(<vscale x 1 x s1>)
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PseudoRET implicit $v0
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...
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‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv32.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=riscv32 -mattr=+v,+m -run-pass=instruction-select \
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# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: splat_zero_nxv1i1
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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; CHECK-LABEL: name: splat_zero_nxv1i1
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; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 -1, 0 /* e8 */
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; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
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; CHECK-NEXT: PseudoRET implicit $v0
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%0:gprb(s32) = G_CONSTANT i32 -1
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%1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
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$v0 = COPY %1(<vscale x 1 x s1>)
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PseudoRET implicit $v0
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...
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---
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name: splat_zero_nxv2i1
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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; CHECK-LABEL: name: splat_zero_nxv2i1
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; CHECK: [[PseudoVMCLR_M_B2_:%[0-9]+]]:vr = PseudoVMCLR_M_B2 -1, 0 /* e8 */
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; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B2_]]
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; CHECK-NEXT: PseudoRET implicit $v0
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%0:gprb(s32) = G_CONSTANT i32 -1
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%1:vrb(<vscale x 2 x s1>) = G_VMCLR_VL %0(s32)
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$v0 = COPY %1(<vscale x 2 x s1>)
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PseudoRET implicit $v0
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...
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---
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name: splat_zero_nxv4i1
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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; CHECK-LABEL: name: splat_zero_nxv4i1
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; CHECK: [[PseudoVMCLR_M_B4_:%[0-9]+]]:vr = PseudoVMCLR_M_B4 -1, 0 /* e8 */
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; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B4_]]
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; CHECK-NEXT: PseudoRET implicit $v0
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%0:gprb(s32) = G_CONSTANT i32 -1
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%1:vrb(<vscale x 4 x s1>) = G_VMCLR_VL %0(s32)
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$v0 = COPY %1(<vscale x 4 x s1>)
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PseudoRET implicit $v0
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...
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---
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name: splat_zero_nxv8i1
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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; CHECK-LABEL: name: splat_zero_nxv8i1
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; CHECK: [[PseudoVMCLR_M_B8_:%[0-9]+]]:vr = PseudoVMCLR_M_B8 -1, 0 /* e8 */
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; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B8_]]
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; CHECK-NEXT: PseudoRET implicit $v0
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%0:gprb(s32) = G_CONSTANT i32 -1
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%1:vrb(<vscale x 8 x s1>) = G_VMCLR_VL %0(s32)
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$v0 = COPY %1(<vscale x 8 x s1>)
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PseudoRET implicit $v0
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...
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---
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name: splat_zero_nxv16i1
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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; CHECK-LABEL: name: splat_zero_nxv16i1
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; CHECK: [[PseudoVMCLR_M_B16_:%[0-9]+]]:vr = PseudoVMCLR_M_B16 -1, 0 /* e8 */
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; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B16_]]
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; CHECK-NEXT: PseudoRET implicit $v0
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%0:gprb(s32) = G_CONSTANT i32 -1
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%1:vrb(<vscale x 16 x s1>) = G_VMCLR_VL %0(s32)
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$v0 = COPY %1(<vscale x 16 x s1>)
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PseudoRET implicit $v0
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89+
...
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---
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name: splat_zero_nxv32i1
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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; CHECK-LABEL: name: splat_zero_nxv32i1
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; CHECK: [[PseudoVMCLR_M_B32_:%[0-9]+]]:vr = PseudoVMCLR_M_B32 -1, 0 /* e8 */
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; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B32_]]
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; CHECK-NEXT: PseudoRET implicit $v0
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%0:gprb(s32) = G_CONSTANT i32 -1
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%1:vrb(<vscale x 32 x s1>) = G_VMCLR_VL %0(s32)
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$v0 = COPY %1(<vscale x 32 x s1>)
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PseudoRET implicit $v0
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...
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---
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name: splat_zero_nxv64i1
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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; CHECK-LABEL: name: splat_zero_nxv64i1
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; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 -1, 0 /* e8 */
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; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]]
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; CHECK-NEXT: PseudoRET implicit $v0
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%0:gprb(s32) = G_CONSTANT i32 -1
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%1:vrb(<vscale x 64 x s1>) = G_VMCLR_VL %0(s32)
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$v0 = COPY %1(<vscale x 64 x s1>)
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PseudoRET implicit $v0
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...
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