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[CodeGen] Use range-based for loops (NFC) (#98104)
1 parent b2ac7f5 commit ef9aba2

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4 files changed

+15
-20
lines changed

4 files changed

+15
-20
lines changed

llvm/lib/CodeGen/InterferenceCache.cpp

Lines changed: 12 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -136,14 +136,12 @@ void InterferenceCache::Entry::update(unsigned MBBNum) {
136136
// Use advanceTo only when possible.
137137
if (PrevPos != Start) {
138138
if (!PrevPos.isValid() || Start < PrevPos) {
139-
for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
140-
RegUnitInfo &RUI = RegUnits[i];
139+
for (RegUnitInfo &RUI : RegUnits) {
141140
RUI.VirtI.find(Start);
142141
RUI.FixedI = RUI.Fixed->find(Start);
143142
}
144143
} else {
145-
for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
146-
RegUnitInfo &RUI = RegUnits[i];
144+
for (RegUnitInfo &RUI : RegUnits) {
147145
RUI.VirtI.advanceTo(Start);
148146
if (RUI.FixedI != RUI.Fixed->end())
149147
RUI.FixedI = RUI.Fixed->advanceTo(RUI.FixedI, Start);
@@ -162,8 +160,8 @@ void InterferenceCache::Entry::update(unsigned MBBNum) {
162160
BI->First = BI->Last = SlotIndex();
163161

164162
// Check for first interference from virtregs.
165-
for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
166-
LiveIntervalUnion::SegmentIter &I = RegUnits[i].VirtI;
163+
for (RegUnitInfo &RUI : RegUnits) {
164+
LiveIntervalUnion::SegmentIter &I = RUI.VirtI;
167165
if (!I.valid())
168166
continue;
169167
SlotIndex StartI = I.start();
@@ -174,9 +172,9 @@ void InterferenceCache::Entry::update(unsigned MBBNum) {
174172
}
175173

176174
// Same thing for fixed interference.
177-
for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
178-
LiveInterval::const_iterator I = RegUnits[i].FixedI;
179-
LiveInterval::const_iterator E = RegUnits[i].Fixed->end();
175+
for (RegUnitInfo &RUI : RegUnits) {
176+
LiveInterval::const_iterator I = RUI.FixedI;
177+
LiveInterval::const_iterator E = RUI.Fixed->end();
180178
if (I == E)
181179
continue;
182180
SlotIndex StartI = I->start;
@@ -213,8 +211,8 @@ void InterferenceCache::Entry::update(unsigned MBBNum) {
213211
}
214212

215213
// Check for last interference in block.
216-
for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
217-
LiveIntervalUnion::SegmentIter &I = RegUnits[i].VirtI;
214+
for (RegUnitInfo &RUI : RegUnits) {
215+
LiveIntervalUnion::SegmentIter &I = RUI.VirtI;
218216
if (!I.valid() || I.start() >= Stop)
219217
continue;
220218
I.advanceTo(Stop);
@@ -229,9 +227,9 @@ void InterferenceCache::Entry::update(unsigned MBBNum) {
229227
}
230228

231229
// Fixed interference.
232-
for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
233-
LiveInterval::iterator &I = RegUnits[i].FixedI;
234-
LiveRange *LR = RegUnits[i].Fixed;
230+
for (RegUnitInfo &RUI : RegUnits) {
231+
LiveInterval::iterator &I = RUI.FixedI;
232+
LiveRange *LR = RUI.Fixed;
235233
if (I == LR->end() || I->start >= Stop)
236234
continue;
237235
I = LR->advanceTo(I, Stop);

llvm/lib/CodeGen/LiveIntervals.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1536,8 +1536,7 @@ void LiveIntervals::handleMoveIntoNewBundle(MachineInstr &BundleStart,
15361536

15371537
// Fix up dead defs
15381538
const SlotIndex Index = getInstructionIndex(BundleStart);
1539-
for (unsigned Idx = 0, E = BundleStart.getNumOperands(); Idx != E; ++Idx) {
1540-
MachineOperand &MO = BundleStart.getOperand(Idx);
1539+
for (MachineOperand &MO : BundleStart.operands()) {
15411540
if (!MO.isReg())
15421541
continue;
15431542
Register Reg = MO.getReg();

llvm/lib/CodeGen/MachineConvergenceVerifier.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -51,8 +51,7 @@ GenericConvergenceVerifier<MachineSSAContext>::findAndCheckConvergenceTokenUsed(
5151
const MachineRegisterInfo &MRI = Context.getFunction()->getRegInfo();
5252
const MachineInstr *TokenDef = nullptr;
5353

54-
for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
55-
const MachineOperand &MO = MI.getOperand(I);
54+
for (const MachineOperand &MO : MI.operands()) {
5655
if (!MO.isReg() || !MO.isUse())
5756
continue;
5857
Register OpReg = MO.getReg();

llvm/lib/CodeGen/MachineInstr.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1041,8 +1041,7 @@ unsigned MachineInstr::getBundleSize() const {
10411041
/// Returns true if the MachineInstr has an implicit-use operand of exactly
10421042
/// the given register (not considering sub/super-registers).
10431043
bool MachineInstr::hasRegisterImplicitUseOperand(Register Reg) const {
1044-
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1045-
const MachineOperand &MO = getOperand(i);
1044+
for (const MachineOperand &MO : operands()) {
10461045
if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
10471046
return true;
10481047
}

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