Skip to content

Commit dd2911d

Browse files
JDevlieghereJDevlieghere
committed
[llvm] Support assembly color highlighting for X86
This patch migrates the X86 backend to WithMarkup (introduced in 77d1032) and adds support for color highlighting. Differential revision: https://reviews.llvm.org/D159241
1 parent 65086ae commit dd2911d

File tree

3 files changed

+36
-40
lines changed

3 files changed

+36
-40
lines changed

‎llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp

Lines changed: 13 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,7 @@ using namespace llvm;
3636
#include "X86GenAsmWriter.inc"
3737

3838
void X86ATTInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const {
39-
OS << markup("<reg:") << '%' << getRegisterName(Reg) << markup(">");
39+
markup(OS, Markup::Register) << '%' << getRegisterName(Reg);
4040
}
4141

4242
void X86ATTInstPrinter::printInst(const MCInst *MI, uint64_t Address,
@@ -386,7 +386,7 @@ void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
386386
} else if (Op.isImm()) {
387387
// Print immediates as signed values.
388388
int64_t Imm = Op.getImm();
389-
O << markup("<imm:") << '$' << formatImm(Imm) << markup(">");
389+
markup(O, Markup::Immediate) << '$' << formatImm(Imm);
390390

391391
// TODO: This should be in a helper function in the base class, so it can
392392
// be used by other printers.
@@ -405,9 +405,9 @@ void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
405405
}
406406
} else {
407407
assert(Op.isExpr() && "unknown operand kind in printOperand");
408-
O << markup("<imm:") << '$';
408+
WithMarkup M = markup(O, Markup::Immediate);
409+
O << '$';
409410
Op.getExpr()->print(O, &MAI);
410-
O << markup(">");
411411
}
412412
}
413413

@@ -427,7 +427,7 @@ void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
427427
const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg);
428428
const MCOperand &DispSpec = MI->getOperand(Op + X86::AddrDisp);
429429

430-
O << markup("<mem:");
430+
WithMarkup M = markup(O, Markup::Memory);
431431

432432
// If this has a segment register, print it.
433433
printOptionalSegReg(MI, Op + X86::AddrSegmentReg, O);
@@ -451,46 +451,40 @@ void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
451451
printOperand(MI, Op + X86::AddrIndexReg, O);
452452
unsigned ScaleVal = MI->getOperand(Op + X86::AddrScaleAmt).getImm();
453453
if (ScaleVal != 1) {
454-
O << ',' << markup("<imm:") << ScaleVal // never printed in hex.
455-
<< markup(">");
454+
O << ',';
455+
markup(O, Markup::Immediate) << ScaleVal; // never printed in hex.
456456
}
457457
}
458458
O << ')';
459459
}
460-
461-
O << markup(">");
462460
}
463461

464462
void X86ATTInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op,
465463
raw_ostream &O) {
466-
O << markup("<mem:");
464+
WithMarkup M = markup(O, Markup::Memory);
467465

468466
// If this has a segment register, print it.
469467
printOptionalSegReg(MI, Op + 1, O);
470468

471469
O << "(";
472470
printOperand(MI, Op, O);
473471
O << ")";
474-
475-
O << markup(">");
476472
}
477473

478474
void X86ATTInstPrinter::printDstIdx(const MCInst *MI, unsigned Op,
479475
raw_ostream &O) {
480-
O << markup("<mem:");
476+
WithMarkup M = markup(O, Markup::Memory);
481477

482478
O << "%es:(";
483479
printOperand(MI, Op, O);
484480
O << ")";
485-
486-
O << markup(">");
487481
}
488482

489483
void X86ATTInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
490484
raw_ostream &O) {
491485
const MCOperand &DispSpec = MI->getOperand(Op);
492486

493-
O << markup("<mem:");
487+
WithMarkup M = markup(O, Markup::Memory);
494488

495489
// If this has a segment register, print it.
496490
printOptionalSegReg(MI, Op + 1, O);
@@ -501,17 +495,15 @@ void X86ATTInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
501495
assert(DispSpec.isExpr() && "non-immediate displacement?");
502496
DispSpec.getExpr()->print(O, &MAI);
503497
}
504-
505-
O << markup(">");
506498
}
507499

508500
void X86ATTInstPrinter::printU8Imm(const MCInst *MI, unsigned Op,
509501
raw_ostream &O) {
510502
if (MI->getOperand(Op).isExpr())
511503
return printOperand(MI, Op, O);
512504

513-
O << markup("<imm:") << '$' << formatImm(MI->getOperand(Op).getImm() & 0xff)
514-
<< markup(">");
505+
markup(O, Markup::Immediate)
506+
<< '$' << formatImm(MI->getOperand(Op).getImm() & 0xff);
515507
}
516508

517509
void X86ATTInstPrinter::printSTiRegOperand(const MCInst *MI, unsigned OpNo,
@@ -520,7 +512,7 @@ void X86ATTInstPrinter::printSTiRegOperand(const MCInst *MI, unsigned OpNo,
520512
unsigned Reg = Op.getReg();
521513
// Override the default printing to print st(0) instead st.
522514
if (Reg == X86::ST0)
523-
OS << markup("<reg:") << "%st(0)" << markup(">");
515+
markup(OS, Markup::Register) << "%st(0)";
524516
else
525517
printRegName(OS, Reg);
526518
}

‎llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -322,23 +322,21 @@ void X86InstPrinterCommon::printPCRelImm(const MCInst *MI, uint64_t Address,
322322

323323
const MCOperand &Op = MI->getOperand(OpNo);
324324
if (Op.isImm()) {
325-
O << markup("<imm:");
326325
if (PrintBranchImmAsAddress) {
327326
uint64_t Target = Address + Op.getImm();
328327
if (MAI.getCodePointerSize() == 4)
329328
Target &= 0xffffffff;
330-
O << formatHex(Target);
329+
markup(O, Markup::Target) << formatHex(Target);
331330
} else
332-
O << formatImm(Op.getImm());
333-
O << markup(">");
331+
markup(O, Markup::Immediate) << formatImm(Op.getImm());
334332
} else {
335333
assert(Op.isExpr() && "unknown pcrel immediate operand");
336334
// If a symbolic branch target was added as a constant expression then print
337335
// that address in hex.
338336
const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
339337
int64_t Address;
340338
if (BranchTarget && BranchTarget->evaluateAsAbsolute(Address)) {
341-
O << markup("<imm:") << formatHex((uint64_t)Address) << markup(">");
339+
markup(O, Markup::Immediate) << formatHex((uint64_t)Address);
342340
} else {
343341
// Otherwise, just print the expression.
344342
Op.getExpr()->print(O, &MAI);

‎llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp

Lines changed: 20 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -34,7 +34,7 @@ using namespace llvm;
3434
#include "X86GenAsmWriter1.inc"
3535

3636
void X86IntelInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const {
37-
OS << markup("<reg:") << getRegisterName(Reg) << markup(">");
37+
markup(OS, Markup::Register) << getRegisterName(Reg);
3838
}
3939

4040
void X86IntelInstPrinter::printInst(const MCInst *MI, uint64_t Address,
@@ -361,7 +361,7 @@ void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
361361
if (Op.isReg()) {
362362
printRegName(O, Op.getReg());
363363
} else if (Op.isImm()) {
364-
O << markup("<imm:") << formatImm((int64_t)Op.getImm()) << markup(">");
364+
markup(O, Markup::Immediate) << formatImm((int64_t)Op.getImm());
365365
} else {
366366
assert(Op.isExpr() && "unknown operand kind in printOperand");
367367
O << "offset ";
@@ -388,7 +388,8 @@ void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
388388
// If this has a segment register, print it.
389389
printOptionalSegReg(MI, Op + X86::AddrSegmentReg, O);
390390

391-
O << markup("<mem:") << '[';
391+
WithMarkup M = markup(O, Markup::Memory);
392+
O << '[';
392393

393394
bool NeedPlus = false;
394395
if (BaseReg.getReg()) {
@@ -419,28 +420,33 @@ void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
419420
DispVal = -DispVal;
420421
}
421422
}
422-
O << markup("<imm:") << formatImm(DispVal) << markup(">");
423+
markup(O, Markup::Immediate) << formatImm(DispVal);
423424
}
424425
}
425426

426-
O << ']' << markup(">");
427+
O << ']';
427428
}
428429

429430
void X86IntelInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op,
430431
raw_ostream &O) {
431432
// If this has a segment register, print it.
432433
printOptionalSegReg(MI, Op + 1, O);
433-
O << markup("<mem:") << '[';
434+
435+
WithMarkup M = markup(O, Markup::Memory);
436+
O << '[';
434437
printOperand(MI, Op, O);
435-
O << ']' << markup(">");
438+
O << ']';
436439
}
437440

438441
void X86IntelInstPrinter::printDstIdx(const MCInst *MI, unsigned Op,
439442
raw_ostream &O) {
440443
// DI accesses are always ES-based.
441-
O << "es:" << markup("<mem:") << '[';
444+
O << "es:";
445+
446+
WithMarkup M = markup(O, Markup::Memory);
447+
O << '[';
442448
printOperand(MI, Op, O);
443-
O << ']' << markup(">");
449+
O << ']';
444450
}
445451

446452
void X86IntelInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
@@ -450,25 +456,25 @@ void X86IntelInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
450456
// If this has a segment register, print it.
451457
printOptionalSegReg(MI, Op + 1, O);
452458

453-
O << markup("<mem:") << '[';
459+
WithMarkup M = markup(O, Markup::Memory);
460+
O << '[';
454461

455462
if (DispSpec.isImm()) {
456-
O << markup("<imm:") << formatImm(DispSpec.getImm()) << markup(">");
463+
markup(O, Markup::Immediate) << formatImm(DispSpec.getImm());
457464
} else {
458465
assert(DispSpec.isExpr() && "non-immediate displacement?");
459466
DispSpec.getExpr()->print(O, &MAI);
460467
}
461468

462-
O << ']' << markup(">");
469+
O << ']';
463470
}
464471

465472
void X86IntelInstPrinter::printU8Imm(const MCInst *MI, unsigned Op,
466473
raw_ostream &O) {
467474
if (MI->getOperand(Op).isExpr())
468475
return MI->getOperand(Op).getExpr()->print(O, &MAI);
469476

470-
O << markup("<imm:") << formatImm(MI->getOperand(Op).getImm() & 0xff)
471-
<< markup(">");
477+
markup(O, Markup::Immediate) << formatImm(MI->getOperand(Op).getImm() & 0xff);
472478
}
473479

474480
void X86IntelInstPrinter::printSTiRegOperand(const MCInst *MI, unsigned OpNo,

0 commit comments

Comments
 (0)