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jwanggit86jwanggit86
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Fix disassembler
1 parent 218f4e7 commit cc05ff1

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9 files changed

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‎llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1207,6 +1207,20 @@ void AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const {
12071207
}
12081208
}
12091209

1210+
// Update RSRC reg to 128b if r128 flag is present.
1211+
int R128Idx =
1212+
AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::r128);
1213+
if (AMDGPU::hasMIMG_R128(STI) && R128Idx != -1 &&
1214+
MI.getOperand(R128Idx).getImm()) {
1215+
// Get first subregister of RSRC
1216+
MCRegister RsrcReg = MI.getOperand(RsrcIdx).getReg();
1217+
MCRegister RsrcSubReg0 = MRI.getSubReg(RsrcReg, AMDGPU::sub0);
1218+
MCRegister NewRsrcReg = MRI.getMatchingSuperReg(
1219+
RsrcSubReg0, AMDGPU::sub0,
1220+
&MRI.getRegClass(AMDGPU::SReg_128_XNULLRegClassID));
1221+
MI.getOperand(RsrcIdx) = MCOperand::createReg(NewRsrcReg);
1222+
}
1223+
12101224
unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf;
12111225
unsigned DstSize = IsGather4 ? 4 : std::max(llvm::popcount(DMask), 1);
12121226

‎llvm/test/MC/Disassembler/AMDGPU/gfx10_mimg.txt

Lines changed: 28 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -43,8 +43,7 @@
4343
# GFX10: image_load_mip_pck_sgn v[16:19], v[8:10], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D unorm dlc ; encoding: [0x88,0x1f,0x14,0xf0,0x08,0x10,0x01,0x00]
4444
0x88,0x1f,0x14,0xf0,0x08,0x10,0x01,0x00
4545

46-
# TODO: This is incorrect: r128 should use a 128-bit register for srsrc
47-
# GFX10: image_load_mip_pck_sgn v[16:19], v[8:10], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D unorm r128 ; encoding: [0x08,0x9f,0x14,0xf0,0x08,0x10,0x01,0x00]
46+
# GFX10: image_load_mip_pck_sgn v[16:19], v[8:10], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm r128 ; encoding: [0x08,0x9f,0x14,0xf0,0x08,0x10,0x01,0x00]
4847
0x08,0x9f,0x14,0xf0,0x08,0x10,0x01,0x00
4948

5049
# GFX10: image_load v16, v[8:9], s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x01,0x00,0xf0,0x08,0x10,0x18,0x00]
@@ -305,6 +304,19 @@
305304
# GFX10: image_atomic_fcmpswap v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm lwe ; encoding: [0x00,0x13,0x76,0xf0,0x02,0x01,0x03,0x00]
306305
0x00,0x13,0x76,0xf0,0x02,0x01,0x03,0x00
307306

307+
# r128
308+
# GFX10: image_load v[252:255], v[2:4], s[0:3] dmask:0xf dim:SQ_RSRC_IMG_3D unorm r128 ; encoding: [0x10,0x9f,0x00,0xf0,0x02,0xfc,0x00,0x00]
309+
0x10,0x9f,0x00,0xf0,0x02,0xfc,0x00,0x00
310+
311+
# GFX10: image_store v16, v[8:9], s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_2D r128 ; encoding: [0x08,0x81,0x20,0xf0,0x08,0x10,0x18,0x00]
312+
0x08,0x81,0x20,0xf0,0x08,0x10,0x18,0x00
313+
314+
# GFX10: image_sample_o v[16:19], v[252:255], s[20:23], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY r128 ; encoding: [0x28,0x8f,0xc0,0xf0,0xfc,0x10,0x25,0x03]
315+
0x28,0x8f,0xc0,0xf0,0xfc,0x10,0x25,0x03
316+
317+
# GFX10: image_atomic_swap v16, v8, s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm r128 ; encoding: [0x00,0x91,0x3c,0xf0,0x08,0x10,0x18,0x00]
318+
0x00,0x91,0x3c,0xf0,0x08,0x10,0x18,0x00
319+
308320
#===------------------------------------------------------------------------===#
309321
# MIMG, NSA address
310322
#===------------------------------------------------------------------------===#
@@ -548,6 +560,19 @@
548560
# GFX10: image_sample_c_cd_cl_o v[16:19], [v8, v9, v10, v11, v12, v13, v14], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x24,0x0f,0xbc,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x00,0x00]
549561
0x24,0x0f,0xbc,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10
550562

563+
# r128
564+
# GFX10: image_atomic_cmpswap v[16:17], [v8, v9], s[96:99] dmask:0x3 dim:SQ_RSRC_IMG_2D r128 ; encoding: [0x0a,0x83,0x40,0xf0,0x08,0x10,0x18,0x00,0x09,0x00,0x00,0x00]
565+
0x0a,0x83,0x40,0xf0,0x08,0x10,0x18,0x00,0x09,0x00,0x00,0x00
566+
567+
# GFX10: image_gather4 v[16:19], [v8, v9, v10], s[20:23], s[100:103] dmask:0x1 dim:SQ_RSRC_IMG_3D r128 ; encoding: [0x12,0x81,0x00,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x00,0x00]
568+
0x12,0x81,0x00,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x00,0x00
569+
570+
# GFX10: image_atomic_umax v16, [v8, v9, v10, v11], s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY r128 ; encoding: [0x3a,0x81,0x5c,0xf0,0x08,0x10,0x18,0x00,0x09,0x0a,0x0b,0x00]
571+
0x3a,0x81,0x5c,0xf0,0x08,0x10,0x18,0x00,0x09,0x0a,0x0b,0x00
572+
573+
# GFX10: image_get_lod v[16:19], [v8, v9, v10], s[20:23], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_3D r128 ; encoding: [0x12,0x8f,0x80,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x00,0x00]
574+
0x12,0x8f,0x80,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x00,0x00
575+
551576
#===------------------------------------------------------------------------===#
552577
# MIMG, Miscellaneous instructions
553578
#===------------------------------------------------------------------------===#
@@ -579,7 +604,7 @@
579604
# GFX10: image_store_mip v1, v[2:3], s[12:19] dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x00,0x24,0xf0,0x02,0x01,0x03,0x00]
580605
0x00,0x00,0x24,0xf0,0x02,0x01,0x03,0x00
581606

582-
# GFX10: image_store_mip_pck v252, v[2:3], s[12:19] dmask:0x1 dim:SQ_RSRC_IMG_1D r128 ; encoding: [0x00,0x81,0x2c,0xf0,0x02,0xfc,0x03,0x00]
607+
# GFX10: image_store_mip_pck v252, v[2:3], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_1D r128 ; encoding: [0x00,0x81,0x2c,0xf0,0x02,0xfc,0x03,0x00]
583608
0x00,0x81,0x2c,0xf0,0x02,0xfc,0x03,0x00
584609

585610
# GFX10: image_atomic_sub v4, v192, s[28:35] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc ; encoding: [0x00,0x31,0x48,0xf0,0xc0,0x04,0x07,0x00]

‎llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_mimg_features.txt

Lines changed: 23 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,7 @@
3939
# GFX11: image_load v0, v255, s[0:7] dmask:0x6 dim:SQ_RSRC_IMG_1D d16 ; encoding: [0x00,0x06,0x02,0xf0,0xff,0x00,0x00,0x00]
4040
0x00,0x06,0x02,0xf0,0xff,0x00,0x00,0x00
4141

42-
# GFX11: image_load v0, v255, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D r128 ; encoding: [0x00,0x81,0x00,0xf0,0xff,0x00,0x00,0x00]
42+
# GFX11: image_load v0, v255, s[0:3] dmask:0x1 dim:SQ_RSRC_IMG_1D r128 ; encoding: [0x00,0x81,0x00,0xf0,0xff,0x00,0x00,0x00]
4343
0x00,0x81,0x00,0xf0,0xff,0x00,0x00,0x00
4444

4545
# GFX11: image_load v0, v[2:3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x04,0x01,0x00,0xf0,0x02,0x00,0x00,0x00]
@@ -217,6 +217,28 @@
217217
# GFX11: image_atomic_xor v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
218218
0x00,0x03,0x50,0xf0,0x01,0x05,0x22,0x00
219219

220+
#===------------------------------------------------------------------------===#
221+
# r128
222+
#===------------------------------------------------------------------------===#
223+
224+
# GFX11: image_load v[1:4], [v2, v3], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm r128 ; encoding: [0x85,0x8f,0x00,0xf0,0x02,0x01,0x01,0x00,0x03,0x00,0x00,0x00]
225+
0x85,0x8f,0x00,0xf0,0x02,0x01,0x01,0x00,0x03,0x00,0x00,0x00
226+
227+
# GFX11: image_load v[1:4], v[2:3], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm r128 ; encoding: [0x84,0x8f,0x00,0xf0,0x02,0x01,0x01,0x00]
228+
0x84,0x8f,0x00,0xf0,0x02,0x01,0x01,0x00
229+
230+
# GFX11: image_store v[0:3], v[254:255], s[96:99] dmask:0xf dim:SQ_RSRC_IMG_2D r128 ; encoding: [0x04,0x8f,0x18,0xf0,0xfe,0x00,0x18,0x00]
231+
0x04,0x8f,0x18,0xf0,0xfe,0x00,0x18,0x00
232+
233+
# GFX11: image_get_resinfo v[4:7], v32, s[96:99] dmask:0xf dim:SQ_RSRC_IMG_3D r128 ; encoding: [0x08,0x8f,0x5c,0xf0,0x20,0x04,0x18,0x00]
234+
0x08,0x8f,0x5c,0xf0,0x20,0x04,0x18,0x00
235+
236+
# GFX11: image_atomic_cmpswap v[4:5], [v32, v1, v2], s[96:99] dmask:0x3 dim:SQ_RSRC_IMG_3D r128 ; encoding: [0x09,0x83,0x2c,0xf0,0x20,0x04,0x18,0x00,0x01,0x02,0x00,0x00]
237+
0x09,0x83,0x2c,0xf0,0x20,0x04,0x18,0x00,0x01,0x02,0x00,0x00
238+
239+
# GFX11: image_gather4 v[64:67], v32, s[4:7], s[100:103] dmask:0x1 dim:SQ_RSRC_IMG_1D r128 ; encoding: [0x00,0x81,0xbc,0xf0,0x20,0x40,0x01,0x64]
240+
0x00,0x81,0xbc,0xf0,0x20,0x40,0x01,0x64
241+
220242

221243
# GFX11: image_sample v[64:66], v32, s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x07,0x6c,0xf0,0x20,0x40,0x01,0x64]
222244
0x00,0x07,0x6c,0xf0,0x20,0x40,0x01,0x64

‎llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vimage.txt

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -108,7 +108,7 @@
108108
# GFX12: image_load v[1:5], [v0, v1], s[16:23] dmask:0xf dim:SQ_RSRC_IMG_2D tfe ; encoding: [0x01,0x00,0xc0,0xd3,0x01,0x20,0x80,0x00,0x00,0x01,0x00,0x00]
109109
0x01,0x00,0xc0,0xd3,0x01,0x20,0x80,0x00,0x00,0x01,0x00,0x00
110110

111-
# GFX12: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D r128 ; encoding: [0x10,0x00,0x40,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
111+
# GFX12: image_load v0, v0, s[0:3] dmask:0x1 dim:SQ_RSRC_IMG_1D r128 ; encoding: [0x10,0x00,0x40,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
112112
0x10,0x00,0x40,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
113113

114114
# GFX12: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x00,0x40,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
@@ -154,7 +154,7 @@
154154
# GFX12: image_load v[0:2], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY th:TH_LOAD_HT scope:SCOPE_SE a16 tfe d16 ; encoding: [0x65,0x00,0xc0,0xd3,0x00,0x10,0xa4,0x00,0x04,0x05,0x00,0x00]
155155
0x65,0x00,0xc0,0xd3,0x00,0x10,0xa4,0x00,0x04,0x05,0x00,0x00
156156

157-
# GFX12: image_load v[0:2], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY th:TH_LOAD_HT scope:SCOPE_SE r128 a16 tfe d16 ; encoding: [0x75,0x00,0xc0,0xd3,0x00,0x10,0xa4,0x00,0x04,0x05,0x00,0x00]
157+
# GFX12: image_load v[0:2], [v4, v5], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY th:TH_LOAD_HT scope:SCOPE_SE r128 a16 tfe d16 ; encoding: [0x75,0x00,0xc0,0xd3,0x00,0x10,0xa4,0x00,0x04,0x05,0x00,0x00]
158158
0x75,0x00,0xc0,0xd3,0x00,0x10,0xa4,0x00,0x04,0x05,0x00,0x00
159159

160160
# GFX12: image_load v[4:7], [v1, v0], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0xc0,0xd3,0x04,0x08,0x00,0x00,0x01,0x00,0x00,0x00]
@@ -370,7 +370,7 @@
370370
# GFX12: image_store v[1:5], [v0, v1], s[16:23] dmask:0xf dim:SQ_RSRC_IMG_2D tfe ; encoding: [0x01,0x80,0xc1,0xd3,0x01,0x20,0x80,0x00,0x00,0x01,0x00,0x00]
371371
0x01,0x80,0xc1,0xd3,0x01,0x20,0x80,0x00,0x00,0x01,0x00,0x00
372372

373-
# GFX12: image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D r128 ; encoding: [0x10,0x80,0x41,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
373+
# GFX12: image_store v0, v0, s[0:3] dmask:0x1 dim:SQ_RSRC_IMG_1D r128 ; encoding: [0x10,0x80,0x41,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
374374
0x10,0x80,0x41,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
375375

376376
# GFX12: image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x80,0x41,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
@@ -550,7 +550,7 @@
550550
# GFX12: image_atomic_swap v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_CASCADE_NT scope:SCOPE_SYS ; encoding: [0x00,0x80,0x42,0xd0,0x00,0x00,0x6c,0x00,0x00,0x00,0x00,0x00]
551551
0x00,0x80,0x42,0xd0,0x00,0x00,0x6c,0x00,0x00,0x00,0x00,0x00
552552

553-
# GFX12: image_atomic_swap v0, [v2, v3], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D r128 ; encoding: [0x11,0x80,0x42,0xd0,0x00,0x08,0x00,0x00,0x02,0x03,0x00,0x00]
553+
# GFX12: image_atomic_swap v0, [v2, v3], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D r128 ; encoding: [0x11,0x80,0x42,0xd0,0x00,0x08,0x00,0x00,0x02,0x03,0x00,0x00]
554554
0x11,0x80,0x42,0xd0,0x00,0x08,0x00,0x00,0x02,0x03,0x00,0x00
555555

556556
# GFX12: image_atomic_swap v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D a16 ; encoding: [0x40,0x80,0x42,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]

‎llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vimage_features.txt

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -99,3 +99,26 @@
9999

100100
# GFX12: image_atomic_xor v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
101101
0x00,0x00,0xc5,0xd0,0x05,0x10,0x80,0x00,0x01,0x00,0x00,0x00
102+
103+
#===------------------------------------------------------------------------===#
104+
# r128
105+
#===------------------------------------------------------------------------===#
106+
107+
# GFX12: image_load v[0:3], v0, s[0:3] dmask:0xf dim:SQ_RSRC_IMG_1D r128 ; encoding: [0x10,0x00,0xc0,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
108+
0x10,0x00,0xc0,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
109+
110+
# GFX12: image_load v[4:7], [v4, v5, v6], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D r128 ; encoding: [0x12,0x00,0xc0,0xd3,0x04,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
111+
0x12,0x00,0xc0,0xd3,0x04,0x10,0x00,0x00,0x04,0x05,0x06,0x00
112+
113+
# GFX12: image_store v[0:3], v0, s[0:3] dmask:0xf dim:SQ_RSRC_IMG_1D r128 ; encoding: [0x10,0x80,0xc1,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
114+
0x10,0x80,0xc1,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
115+
116+
# GFX12: image_get_resinfo v4, v32, s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_1D r128 ; encoding: [0x10,0xc0,0x45,0xd0,0x04,0xc0,0x00,0x00,0x20,0x00,0x00,0x00]
117+
0x10,0xc0,0x45,0xd0,0x04,0xc0,0x00,0x00,0x20,0x00,0x00,0x00
118+
119+
# GFX12: image_atomic_swap v[1:2], [v4, v5, v6], s[8:11] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY r128 ; encoding: [0x15,0x80,0xc2,0xd0,0x01,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
120+
0x15,0x80,0xc2,0xd0,0x01,0x10,0x00,0x00,0x04,0x05,0x06,0x00
121+
122+
# GFX12: image_atomic_swap v2, v4, s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D r128 ; encoding: [0x10,0x80,0x42,0xd0,0x02,0x10,0x00,0x00,0x04,0x00,0x00,0x00]
123+
0x10,0x80,0x42,0xd0,0x02,0x10,0x00,0x00,0x04,0x00,0x00,0x00
124+

‎llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vsample.txt

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -39,8 +39,7 @@
3939
# GFX12: image_sample v[22:24], v25, s[24:31], s[76:79] dmask:0xd dim:SQ_RSRC_IMG_1D unorm ; encoding: [0x00,0xe0,0x46,0xe7,0x16,0x30,0x00,0x26,0x19,0x00,0x00,0x00]
4040
0x00,0xe0,0x46,0xe7,0x16,0x30,0x00,0x26,0x19,0x00,0x00,0x00
4141

42-
# FIXME: This test is incorrect because r128 assumes a 128-bit SRSRC.
43-
# GFX12: image_sample v[22:24], v25, s[24:31], s[76:79] dmask:0xd dim:SQ_RSRC_IMG_1D r128 ; encoding: [0x10,0xc0,0x46,0xe7,0x16,0x30,0x00,0x26,0x19,0x00,0x00,0x00]
42+
# GFX12: image_sample v[22:24], v25, s[24:27], s[76:79] dmask:0xd dim:SQ_RSRC_IMG_1D r128 ; encoding: [0x10,0xc0,0x46,0xe7,0x16,0x30,0x00,0x26,0x19,0x00,0x00,0x00]
4443
0x10,0xc0,0x46,0xe7,0x16,0x30,0x00,0x26,0x19,0x00,0x00,0x00
4544

4645
# GFX12: image_sample v26, [v27, v28], s[28:35], s[72:75] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0xc0,0x46,0xe4,0x1a,0x38,0x00,0x24,0x1b,0x1c,0x00,0x00]
@@ -94,8 +93,7 @@
9493
# GFX12: image_sample v[34:35], v37, s[36:43], s[64:67] dmask:0x3 dim:SQ_RSRC_IMG_1D lwe ; encoding: [0x00,0xc0,0xc6,0xe4,0x22,0x49,0x00,0x20,0x25,0x00,0x00,0x00]
9594
0x00,0xc0,0xc6,0xe4,0x22,0x49,0x00,0x20,0x25,0x00,0x00,0x00
9695

97-
# FIXME: This test is incorrect because r128 assumes a 128-bit SRSRC.
98-
# GFX12: image_sample v[38:39], [v40, v41], s[40:47], s[60:63] dmask:0xc dim:SQ_RSRC_IMG_CUBE unorm th:TH_LOAD_HT scope:SCOPE_DEV r128 a16 tfe lwe d16 ; encoding: [0x7b,0xe0,0x06,0xe7,0x26,0x51,0x28,0x1e,0x28,0x29,0x00,0x00]
96+
# GFX12: image_sample v[38:39], [v40, v41], s[40:43], s[60:63] dmask:0xc dim:SQ_RSRC_IMG_CUBE unorm th:TH_LOAD_HT scope:SCOPE_DEV r128 a16 tfe lwe d16 ; encoding: [0x7b,0xe0,0x06,0xe7,0x26,0x51,0x28,0x1e,0x28,0x29,0x00,0x00]
9997
0x7b,0xe0,0x06,0xe7,0x26,0x51,0x28,0x1e,0x28,0x29,0x00,0x00
10098

10199
# GFX12: image_sample_d v64, [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x00,0x47,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
@@ -461,8 +459,7 @@
461459
# GFX12: image_gather4 v[0:3], [v4, v5], s[0:7], s[100:103] dmask:0x8 dim:SQ_RSRC_IMG_2D unorm ; encoding: [0x01,0xe0,0x0b,0xe6,0x00,0x00,0x00,0x32,0x04,0x05,0x00,0x00]
462460
0x01,0xe0,0x0b,0xe6,0x00,0x00,0x00,0x32,0x04,0x05,0x00,0x00
463461

464-
# FIXME: This test is incorrect because r128 assumes a 128-bit SRSRC.
465-
# GFX12: image_gather4 v[6:9], [v10, v11], s[8:15], s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_2D r128 ; encoding: [0x11,0xc0,0x4b,0xe4,0x06,0x10,0x00,0x30,0x0a,0x0b,0x00,0x00]
462+
# GFX12: image_gather4 v[6:9], [v10, v11], s[8:11], s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_2D r128 ; encoding: [0x11,0xc0,0x4b,0xe4,0x06,0x10,0x00,0x30,0x0a,0x0b,0x00,0x00]
466463
0x11,0xc0,0x4b,0xe4,0x06,0x10,0x00,0x30,0x0a,0x0b,0x00,0x00
467464

468465
# GFX12: image_gather4 v[12:15], [v16, v17], s[16:23], s[92:95] dmask:0x2 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0xc0,0x8b,0xe4,0x0c,0x20,0x00,0x2e,0x10,0x11,0x00,0x00]

‎llvm/test/MC/Disassembler/AMDGPU/gfx8_mimg_features.txt

Lines changed: 15 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -30,8 +30,9 @@
3030
0x00 0x11 0x20 0xf0 0x01 0x00 0x00 0x00
3131

3232
# Test all modifiers
33-
# FIXME: This test is incorrect because r128 assumes a 128-bit SRSRC.
34-
# VI: image_load v[5:6], v1, s[8:15] dmask:0x1 unorm glc slc r128 tfe lwe da d16 ; encoding: [0x00,0xf1,0x03,0xf2,0x01,0x05,0x02,0x80]
33+
34+
# Test r128
35+
# VI: image_load v[5:6], v1, s[8:11] dmask:0x1 unorm glc slc r128 tfe lwe da d16 ; encoding: [0x00,0xf1,0x03,0xf2,0x01,0x05,0x02,0x80]
3536
0x00,0xf1,0x03,0xf2,0x01,0x05,0x02,0x80
3637

3738
# Test dmask == 0
@@ -48,6 +49,9 @@
4849
# VI: image_load v255, v0, s[0:7] dmask:0x3 unorm ; encoding: [0x00,0x13,0x00,0xf0,0x00,0xff,0x00,0x00]
4950
0x00 0x13 0x00 0xf0 0x00 0xff 0x00 0x00
5051

52+
# VI: image_store v[0:1], v2, s[0:3] dmask:0x3 unorm r128 ; encoding: [0x00,0x93,0x20,0xf0,0x02,0x00,0x00,0x00]
53+
0x00,0x93,0x20,0xf0,0x02,0x00,0x00,0x00
54+
5155
#===------------------------------------------------------------------------===#
5256
# Image load/store: packed/unpacked d16
5357
#===------------------------------------------------------------------------===#
@@ -147,6 +151,9 @@
147151
# GFX81: image_sample v[193:194], v237, s[28:35], s[4:7] dmask:0xf d16 ; encoding: [0x00,0x0f,0x80,0xf0,0xed,0xc1,0x27,0x80]
148152
0x00,0x0f,0x80,0xf0,0xed,0xc1,0x27,0x80
149153

154+
# VI: image_sample v[193:195], v237, s[28:31], s[4:7] dmask:0x7 unorm r128 ; encoding: [0x00,0x97,0x80,0xf0,0xed,0xc1,0x27,0x00]
155+
0x00,0x97,0x80,0xf0,0xed,0xc1,0x27,0x00
156+
150157
#===------------------------------------------------------------------------===#
151158
# Image atomics
152159
#===------------------------------------------------------------------------===#
@@ -178,12 +185,18 @@
178185
# VI: image_atomic_add v[5:6], v1, s[8:15] dmask:0x3 unorm ; encoding: [0x00,0x13,0x48,0xf0,0x01,0x05,0x02,0x00]
179186
0x00,0x13,0x48,0xf0,0x01,0x05,0x02,0x00
180187

188+
# VI: image_atomic_add v5, v1, s[8:11] dmask:0x1 unorm r128 ; encoding: [0x00,0x91,0x48,0xf0,0x01,0x05,0x02,0x00]
189+
0x00,0x91,0x48,0xf0,0x01,0x05,0x02,0x00
190+
181191
# VI: image_atomic_cmpswap v[5:6], v1, s[8:15] dmask:0x3 unorm ; encoding: [0x00,0x13,0x44,0xf0,0x01,0x05,0x02,0x00]
182192
0x00,0x13,0x44,0xf0,0x01,0x05,0x02,0x00
183193

184194
# VI: image_atomic_cmpswap v[5:8], v1, s[8:15] dmask:0xf unorm ; encoding: [0x00,0x1f,0x44,0xf0,0x01,0x05,0x02,0x00]
185195
0x00,0x1f,0x44,0xf0,0x01,0x05,0x02,0x00
186196

197+
# VI: image_atomic_cmpswap v[5:8], v1, s[8:11] dmask:0xf unorm r128 ; encoding: [0x00,0x9f,0x44,0xf0,0x01,0x05,0x02,0x00]
198+
0x00,0x9f,0x44,0xf0,0x01,0x05,0x02,0x00
199+
187200
# VI: image_atomic_add v[5:6], v1, s[8:15] dmask:0x1 tfe
188201
0x00,0x01,0x49,0xf0,0x01,0x05,0x02,0x00
189202

‎llvm/test/MC/Disassembler/AMDGPU/gfx90a_mimg.txt

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -74,3 +74,10 @@
7474

7575
0x00,0x01,0x80,0xf0,0x00,0x05,0x62,0x00
7676
# GFX90A: image_sample v5, v0, s[8:15], s[12:15] dmask:0x1 ; encoding: [0x00,0x01,0x80,0xf0,0x00,0x05,0x62,0x00]
77+
78+
# Rsrc reg is 256b regardless of a16
79+
# GFX90A: image_sample v6, v0, s[8:15], s[12:15] dmask:0x1 a16 ; encoding: [0x00,0x81,0x80,0xf0,0x00,0x06,0x62,0x00]
80+
0x00,0x81,0x80,0xf0,0x00,0x06,0x62,0x00
81+
82+
# GFX90A: image_sample v[6:7], v0, s[8:15], s[12:15] dmask:0x3 a16 ; encoding: [0x00,0x83,0x80,0xf0,0x00,0x06,0x62,0x00]
83+
0x00,0x83,0x80,0xf0,0x00,0x06,0x62,0x00

‎llvm/test/MC/Disassembler/AMDGPU/gfx9_mimg_features.txt

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -81,3 +81,6 @@
8181
# GFX900: image_atomic_xor v[5:7], v1, s[8:15] dmask:0x3 tfe
8282
0x00,0x03,0x69,0xf0,0x01,0x05,0x02,0x00
8383

84+
# Rsrc reg size is 256b regardless of a16
85+
# GFX900: image_atomic_xor v[5:6], v1, s[8:15] dmask:0x3 a16
86+
0x00,0x83,0x68,0xf0,0x01,0x05,0x02,0x00

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