[AArch64] Fix subtarget features for tests. NFC

These tests were using instructions that require feature predicates that
were not enabled.

Author: davemgreen

llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll

@@ -3,8 +3,8 @@
 ; RUN: llc < %s -mtriple=arm64-apple-ios -global-isel -global-isel-abort=1 -O0 -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK-NOLSE,CHECK-NOLSE-O0
 ; RUN: llc < %s -mtriple=arm64-apple-ios -global-isel -global-isel-abort=1 -mcpu=apple-a13 -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK-LSE-O1
 ; RUN: llc < %s -mtriple=arm64-apple-ios -global-isel -global-isel-abort=1 -mcpu=apple-a13 -O0 -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK-LSE-O0
-; RUN: llc < %s -mtriple=arm64-apple-ios -global-isel -global-isel-abort=1 -mattr=+ldapr -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK-LDAPR-O1
-; RUN: llc < %s -mtriple=arm64-apple-ios -global-isel -global-isel-abort=1 -mattr=+ldapr -O0 -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK-LDAPR-O0
+; RUN: llc < %s -mtriple=arm64-apple-ios -global-isel -global-isel-abort=1 -mattr=+rcpc,+ldapr -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK-LDAPR-O1
+; RUN: llc < %s -mtriple=arm64-apple-ios -global-isel -global-isel-abort=1 -mattr=+rcpc,+ldapr -O0 -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK-LDAPR-O0
 
 define i32 @val_compare_and_swap(i32* %p, i32 %cmp, i32 %new) #0 {
 ; CHECK-NOLSE-O1-LABEL: val_compare_and_swap:

llvm/test/CodeGen/AArch64/GlobalISel/regbank-extract.mir

@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -O0 -run-pass=regbankselect %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-unknown-unknown -mattr=+lse -verify-machineinstrs -O0 -run-pass=regbankselect %s -o - | FileCheck %s
 ---
 name:            extract_s64_s128
 alignment:       4

llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-crypto-aesmc.mir

@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64-- -mattr=+fuse-aes -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-- -mattr=+aes,+fuse-aes -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
 
 ---
 # Check that we select the aarch64_crypto_aesmc and aarch64_crypto_aese

llvm/test/CodeGen/AArch64/addg_subg.mir

@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=aarch64 -run-pass=prologepilog,aarch64-expand-pseudo %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -mattr=+mte -run-pass=prologepilog,aarch64-expand-pseudo %s -o - | FileCheck %s
 
 # CHECK: renamable $x8 = IRG $sp, $xzr
 

llvm/test/CodeGen/AArch64/arm64-neon-3vdiff.ll

@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon,+aes | FileCheck %s
 
 declare <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8>, <8 x i8>)
 declare <16 x i8> @llvm.aarch64.neon.pmull64(i64, i64) #5

llvm/test/CodeGen/AArch64/arm64-vmul.ll

@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -mattr=+aes | FileCheck %s
 
 define <8 x i16> @smull8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ; CHECK-LABEL: smull8h:

llvm/test/CodeGen/AArch64/atomic-ops-ldapr.ll

@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+ldapr -fast-isel=0 -global-isel=false -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+ldapr -fast-isel=1 -global-isel=false -verify-machineinstrs < %s | FileCheck %s --check-prefix=FAST-ISEL
+; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+rcpc,+ldapr -fast-isel=0 -global-isel=false -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+rcpc,+ldapr -fast-isel=1 -global-isel=false -verify-machineinstrs < %s | FileCheck %s --check-prefix=FAST-ISEL
 
 define i8 @test_load_8_acq(i8* %addr) {
 ; CHECK-LABEL: test_load_8_acq:

llvm/test/CodeGen/AArch64/branch-target-enforcement.mir

@@ -1,4 +1,4 @@
-# RUN: llc -run-pass=aarch64-branch-targets %s -o - | FileCheck %s
+# RUN: llc -run-pass=aarch64-branch-targets -mattr=+pauth %s -o - | FileCheck %s
 --- |
   target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
   target triple = "aarch64-arm-none-eabi"

llvm/test/CodeGen/AArch64/dag-combine-lifetime-end-store-typesize.ll

@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=aarch64-- < %s
+; RUN: llc -mtriple=aarch64-- -mattr=+sve < %s
 
 ; This regression test is defending against using the wrong interface for TypeSize.
 ; This issue appeared in DAGCombiner::visitLIFETIME_END when visiting a LIFETIME_END

llvm/test/CodeGen/AArch64/ldst-opt-mte-with-dbg.mir

@@ -1,8 +1,8 @@
 # Strip out debug info, then run ldst-opt with limit=1.
-# RUN: llc -aarch64-load-store-scan-limit=1 -mtriple=aarch64-none-linux-gnu -run-pass mir-strip-debug,aarch64-ldst-opt -mir-strip-debugify-only=0 -verify-machineinstrs  -o - %s | FileCheck %s
+# RUN: llc -aarch64-load-store-scan-limit=1 -mtriple=aarch64-none-linux-gnu -mattr=+mte -run-pass mir-strip-debug,aarch64-ldst-opt -mir-strip-debugify-only=0 -verify-machineinstrs  -o - %s | FileCheck %s
 #
 # Run ldst-opt with limit=1, then strip out debug info.
-# RUN: llc -aarch64-load-store-scan-limit=1 -mtriple=aarch64-none-linux-gnu -run-pass aarch64-ldst-opt,mir-strip-debug -mir-strip-debugify-only=0 -verify-machineinstrs  -o - %s | FileCheck %s
+# RUN: llc -aarch64-load-store-scan-limit=1 -mtriple=aarch64-none-linux-gnu -mattr=+mte -run-pass aarch64-ldst-opt,mir-strip-debug -mir-strip-debugify-only=0 -verify-machineinstrs  -o - %s | FileCheck %s
 ---
 
 ### STG and its offset limits

llvm/test/CodeGen/AArch64/ldst-opt-mte.mir

@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass aarch64-ldst-opt  -verify-machineinstrs  -o - %s | FileCheck %s
-# RUN: llc -debugify-and-strip-all-safe -mtriple=aarch64-none-linux-gnu -run-pass aarch64-ldst-opt  -verify-machineinstrs  -o - %s | FileCheck %s
+# RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+mte -run-pass aarch64-ldst-opt  -verify-machineinstrs  -o - %s | FileCheck %s
+# RUN: llc -debugify-and-strip-all-safe -mtriple=aarch64-none-linux-gnu -mattr=+mte -run-pass aarch64-ldst-opt  -verify-machineinstrs  -o - %s | FileCheck %s
 ---
 
 ### STG and its offset limits

llvm/test/CodeGen/AArch64/neon-vmull-high-p64.ll

@@ -1,4 +1,4 @@
-; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon,+aes | FileCheck %s
 
 ; This test checks that pmull2 instruction is used for vmull_high_p64 intrinsic.
 ; There are two extraction operations located in different basic blocks:

llvm/test/CodeGen/AArch64/speculation-hardening-sls.mir

@@ -1,10 +1,10 @@
 # RUN: llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu \
 # RUN:     -start-before aarch64-sls-hardening -o - %s \
-# RUN:     -mattr=harden-sls-retbr \
+# RUN:     -mattr=+pauth,+harden-sls-retbr \
 # RUN:   | FileCheck %s --check-prefixes=CHECK,ISBDSB
 # RUN: llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu \
 # RUN:     -start-before aarch64-sls-hardening -o - %s \
-# RUN:     -mattr=harden-sls-retbr -mattr=+sb \
+# RUN:     -mattr=+pauth,+harden-sls-retbr -mattr=+sb \
 # RUN:   | FileCheck %s --check-prefixes=CHECK,SB
 
 # Check that the SLS hardening pass also protects BRA* indirect branches that

llvm/test/CodeGen/AArch64/sve-ptest-removal-whilege.mir

@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve -run-pass=peephole-opt -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve2 -run-pass=peephole-opt -verify-machineinstrs %s -o - | FileCheck %s
 
 # Test instruction sequences where PTEST is redundant and thus gets removed.
 ---

llvm/test/CodeGen/AArch64/sve-ptest-removal-whilegt.mir

@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve -run-pass=peephole-opt -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve2 -run-pass=peephole-opt -verify-machineinstrs %s -o - | FileCheck %s
 
 # Test instruction sequences where PTEST is redundant and thus gets removed.
 ---

llvm/test/CodeGen/AArch64/sve-ptest-removal-whilehi.mir

@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve -run-pass=peephole-opt -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve2 -run-pass=peephole-opt -verify-machineinstrs %s -o - | FileCheck %s
 
 # Test instruction sequences where PTEST is redundant and thus gets removed.
 ---

llvm/test/CodeGen/AArch64/sve-ptest-removal-whilehs.mir

@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve -run-pass=peephole-opt -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve2 -run-pass=peephole-opt -verify-machineinstrs %s -o - | FileCheck %s
 
 # Test instruction sequences where PTEST is redundant and thus gets removed.
 ---

llvm/test/CodeGen/AArch64/sve-ptest-removal-whilerw.mir

@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve -run-pass=peephole-opt -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve2 -run-pass=peephole-opt -verify-machineinstrs %s -o - | FileCheck %s
 
 # Test instruction sequences where PTEST is redundant and thus gets removed.
 ---

llvm/test/CodeGen/AArch64/sve-ptest-removal-whilewr.mir

@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve -run-pass=peephole-opt -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve2 -run-pass=peephole-opt -verify-machineinstrs %s -o - | FileCheck %s
 
 # Test instruction sequences where PTEST is redundant and thus gets removed.
 ---

llvm/unittests/Target/AArch64/InstSizes.cpp

@@ -14,7 +14,7 @@ namespace {
 std::unique_ptr<LLVMTargetMachine> createTargetMachine() {
   auto TT(Triple::normalize("aarch64--"));
   std::string CPU("generic");
-  std::string FS("");
+  std::string FS("+pauth,+mops,+mte");
 
   LLVMInitializeAArch64TargetInfo();
   LLVMInitializeAArch64Target();