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[RISCV] Add SEXT_INREG patterns for Xqcibm ext instruction (#140192)
Handle sign_extend_inreg from i1/i8/i16
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lines changed

4 files changed

+244
-1
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -310,12 +310,13 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
310310
setOperationAction(ISD::VASTART, MVT::Other, Custom);
311311
setOperationAction({ISD::VAARG, ISD::VACOPY, ISD::VAEND}, MVT::Other, Expand);
312312

313-
if (!Subtarget.hasVendorXTHeadBb())
313+
if (!Subtarget.hasVendorXTHeadBb() && !Subtarget.hasVendorXqcibm())
314314
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
315315

316316
setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom);
317317

318318
if (!Subtarget.hasStdExtZbb() && !Subtarget.hasVendorXTHeadBb() &&
319+
!Subtarget.hasVendorXqcibm() &&
319320
!(Subtarget.hasVendorXCValu() && !Subtarget.is64Bit()))
320321
setOperationAction(ISD::SIGN_EXTEND_INREG, {MVT::i8, MVT::i16}, Expand);
321322

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2704,6 +2704,9 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
27042704
case RISCVOp::OPERAND_UIMM5_NONZERO:
27052705
Ok = isUInt<5>(Imm) && (Imm != 0);
27062706
break;
2707+
case RISCVOp::OPERAND_UIMM5_PLUS1:
2708+
Ok = (isUInt<5>(Imm) && (Imm != 0)) || (Imm == 32);
2709+
break;
27072710
case RISCVOp::OPERAND_UIMM6_LSB0:
27082711
Ok = isShiftedUInt<5, 1>(Imm);
27092712
break;

‎llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1434,6 +1434,12 @@ def : SelectQCbi<SETULT, uimm16nonzero, Select_GPR_Using_CC_Uimm16NonZero>;
14341434
def : SelectQCbi<SETUGE, uimm16nonzero, Select_GPR_Using_CC_Uimm16NonZero>;
14351435
} // let Predicates = [HasVendorXqcibi, IsRV32], AddedComplexity = 2
14361436

1437+
let Predicates = [HasVendorXqcibm, IsRV32] in {
1438+
def : Pat<(sext_inreg (i32 GPR:$rs1), i16), (QC_EXT GPR:$rs1, 16, 0)>;
1439+
def : Pat<(sext_inreg (i32 GPR:$rs1), i8), (QC_EXT GPR:$rs1, 8, 0)>;
1440+
def : Pat<(sext_inreg (i32 GPR:$rs1), i1), (QC_EXT GPR:$rs1, 1, 0)>;
1441+
} // Predicates = [HasVendorXqcibm, IsRV32]
1442+
14371443
let Predicates = [HasVendorXqciint, IsRV32] in
14381444
def : Pat<(riscv_mileaveret_glue), (QC_C_MILEAVERET)>;
14391445

‎llvm/test/CodeGen/RISCV/xqcibm-extract.ll

Lines changed: 233 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,233 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2+
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3+
; RUN: | FileCheck %s -check-prefixes=RV32I
4+
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcibm -verify-machineinstrs < %s \
5+
; RUN: | FileCheck %s -check-prefixes=RV32XQCIBM
6+
7+
define i32 @sexti1_i32(i1 %a) nounwind {
8+
; RV32I-LABEL: sexti1_i32:
9+
; RV32I: # %bb.0:
10+
; RV32I-NEXT: slli a0, a0, 31
11+
; RV32I-NEXT: srai a0, a0, 31
12+
; RV32I-NEXT: ret
13+
;
14+
; RV32XQCIBM-LABEL: sexti1_i32:
15+
; RV32XQCIBM: # %bb.0:
16+
; RV32XQCIBM-NEXT: qc.ext a0, a0, 1, 0
17+
; RV32XQCIBM-NEXT: ret
18+
%sext = sext i1 %a to i32
19+
ret i32 %sext
20+
}
21+
22+
define i32 @sexti1_i32_2(i32 %a) {
23+
; RV32I-LABEL: sexti1_i32_2:
24+
; RV32I: # %bb.0:
25+
; RV32I-NEXT: slli a0, a0, 31
26+
; RV32I-NEXT: srai a0, a0, 31
27+
; RV32I-NEXT: ret
28+
;
29+
; RV32XQCIBM-LABEL: sexti1_i32_2:
30+
; RV32XQCIBM: # %bb.0:
31+
; RV32XQCIBM-NEXT: qc.ext a0, a0, 1, 0
32+
; RV32XQCIBM-NEXT: ret
33+
%shl = shl i32 %a, 31
34+
%shr = ashr exact i32 %shl, 31
35+
ret i32 %shr
36+
}
37+
38+
39+
define i32 @sexti8_i32(i8 %a) nounwind {
40+
; RV32I-LABEL: sexti8_i32:
41+
; RV32I: # %bb.0:
42+
; RV32I-NEXT: slli a0, a0, 24
43+
; RV32I-NEXT: srai a0, a0, 24
44+
; RV32I-NEXT: ret
45+
;
46+
; RV32XQCIBM-LABEL: sexti8_i32:
47+
; RV32XQCIBM: # %bb.0:
48+
; RV32XQCIBM-NEXT: qc.ext a0, a0, 8, 0
49+
; RV32XQCIBM-NEXT: ret
50+
%sext = sext i8 %a to i32
51+
ret i32 %sext
52+
}
53+
54+
define i32 @sexti8_i32_2(i32 %a) {
55+
; RV32I-LABEL: sexti8_i32_2:
56+
; RV32I: # %bb.0:
57+
; RV32I-NEXT: slli a0, a0, 24
58+
; RV32I-NEXT: srai a0, a0, 24
59+
; RV32I-NEXT: ret
60+
;
61+
; RV32XQCIBM-LABEL: sexti8_i32_2:
62+
; RV32XQCIBM: # %bb.0:
63+
; RV32XQCIBM-NEXT: qc.ext a0, a0, 8, 0
64+
; RV32XQCIBM-NEXT: ret
65+
%shl = shl i32 %a, 24
66+
%shr = ashr exact i32 %shl, 24
67+
ret i32 %shr
68+
}
69+
70+
define i32 @sexti16_i32(i16 %a) nounwind {
71+
; RV32I-LABEL: sexti16_i32:
72+
; RV32I: # %bb.0:
73+
; RV32I-NEXT: slli a0, a0, 16
74+
; RV32I-NEXT: srai a0, a0, 16
75+
; RV32I-NEXT: ret
76+
;
77+
; RV32XQCIBM-LABEL: sexti16_i32:
78+
; RV32XQCIBM: # %bb.0:
79+
; RV32XQCIBM-NEXT: qc.ext a0, a0, 16, 0
80+
; RV32XQCIBM-NEXT: ret
81+
%sext = sext i16 %a to i32
82+
ret i32 %sext
83+
}
84+
85+
define i32 @sexti16_i32_2(i32 %a) {
86+
; RV32I-LABEL: sexti16_i32_2:
87+
; RV32I: # %bb.0:
88+
; RV32I-NEXT: slli a0, a0, 16
89+
; RV32I-NEXT: srai a0, a0, 16
90+
; RV32I-NEXT: ret
91+
;
92+
; RV32XQCIBM-LABEL: sexti16_i32_2:
93+
; RV32XQCIBM: # %bb.0:
94+
; RV32XQCIBM-NEXT: qc.ext a0, a0, 16, 0
95+
; RV32XQCIBM-NEXT: ret
96+
%shl = shl i32 %a, 16
97+
%shr = ashr exact i32 %shl, 16
98+
ret i32 %shr
99+
}
100+
101+
define i64 @sexti1_i64(i64 %a) {
102+
; RV32I-LABEL: sexti1_i64:
103+
; RV32I: # %bb.0:
104+
; RV32I-NEXT: slli a0, a0, 31
105+
; RV32I-NEXT: srai a0, a0, 31
106+
; RV32I-NEXT: mv a1, a0
107+
; RV32I-NEXT: ret
108+
;
109+
; RV32XQCIBM-LABEL: sexti1_i64:
110+
; RV32XQCIBM: # %bb.0:
111+
; RV32XQCIBM-NEXT: qc.ext a0, a0, 1, 0
112+
; RV32XQCIBM-NEXT: mv a1, a0
113+
; RV32XQCIBM-NEXT: ret
114+
%shl = shl i64 %a, 63
115+
%shr = ashr exact i64 %shl, 63
116+
ret i64 %shr
117+
}
118+
119+
define i64 @sexti1_i64_2(i1 %a) {
120+
; RV32I-LABEL: sexti1_i64_2:
121+
; RV32I: # %bb.0:
122+
; RV32I-NEXT: slli a0, a0, 31
123+
; RV32I-NEXT: srai a0, a0, 31
124+
; RV32I-NEXT: mv a1, a0
125+
; RV32I-NEXT: ret
126+
;
127+
; RV32XQCIBM-LABEL: sexti1_i64_2:
128+
; RV32XQCIBM: # %bb.0:
129+
; RV32XQCIBM-NEXT: qc.ext a0, a0, 1, 0
130+
; RV32XQCIBM-NEXT: mv a1, a0
131+
; RV32XQCIBM-NEXT: ret
132+
%1 = sext i1 %a to i64
133+
ret i64 %1
134+
}
135+
136+
define i64 @sexti8_i64(i64 %a) {
137+
; RV32I-LABEL: sexti8_i64:
138+
; RV32I: # %bb.0:
139+
; RV32I-NEXT: slli a1, a0, 24
140+
; RV32I-NEXT: srai a0, a1, 24
141+
; RV32I-NEXT: srai a1, a1, 31
142+
; RV32I-NEXT: ret
143+
;
144+
; RV32XQCIBM-LABEL: sexti8_i64:
145+
; RV32XQCIBM: # %bb.0:
146+
; RV32XQCIBM-NEXT: qc.ext a0, a0, 8, 0
147+
; RV32XQCIBM-NEXT: srai a1, a0, 31
148+
; RV32XQCIBM-NEXT: ret
149+
%shl = shl i64 %a, 56
150+
%shr = ashr exact i64 %shl, 56
151+
ret i64 %shr
152+
}
153+
154+
define i64 @sexti8_i64_2(i8 %a) {
155+
; RV32I-LABEL: sexti8_i64_2:
156+
; RV32I: # %bb.0:
157+
; RV32I-NEXT: slli a1, a0, 24
158+
; RV32I-NEXT: srai a0, a1, 24
159+
; RV32I-NEXT: srai a1, a1, 31
160+
; RV32I-NEXT: ret
161+
;
162+
; RV32XQCIBM-LABEL: sexti8_i64_2:
163+
; RV32XQCIBM: # %bb.0:
164+
; RV32XQCIBM-NEXT: qc.ext a0, a0, 8, 0
165+
; RV32XQCIBM-NEXT: srai a1, a0, 31
166+
; RV32XQCIBM-NEXT: ret
167+
%1 = sext i8 %a to i64
168+
ret i64 %1
169+
}
170+
171+
define i64 @sexti16_i64(i64 %a) {
172+
; RV32I-LABEL: sexti16_i64:
173+
; RV32I: # %bb.0:
174+
; RV32I-NEXT: slli a1, a0, 16
175+
; RV32I-NEXT: srai a0, a1, 16
176+
; RV32I-NEXT: srai a1, a1, 31
177+
; RV32I-NEXT: ret
178+
;
179+
; RV32XQCIBM-LABEL: sexti16_i64:
180+
; RV32XQCIBM: # %bb.0:
181+
; RV32XQCIBM-NEXT: qc.ext a0, a0, 16, 0
182+
; RV32XQCIBM-NEXT: srai a1, a0, 31
183+
; RV32XQCIBM-NEXT: ret
184+
%shl = shl i64 %a, 48
185+
%shr = ashr exact i64 %shl, 48
186+
ret i64 %shr
187+
}
188+
189+
define i64 @sexti16_i64_2(i16 %a) {
190+
; RV32I-LABEL: sexti16_i64_2:
191+
; RV32I: # %bb.0:
192+
; RV32I-NEXT: slli a1, a0, 16
193+
; RV32I-NEXT: srai a0, a1, 16
194+
; RV32I-NEXT: srai a1, a1, 31
195+
; RV32I-NEXT: ret
196+
;
197+
; RV32XQCIBM-LABEL: sexti16_i64_2:
198+
; RV32XQCIBM: # %bb.0:
199+
; RV32XQCIBM-NEXT: qc.ext a0, a0, 16, 0
200+
; RV32XQCIBM-NEXT: srai a1, a0, 31
201+
; RV32XQCIBM-NEXT: ret
202+
%1 = sext i16 %a to i64
203+
ret i64 %1
204+
}
205+
206+
define i64 @sexti32_i64(i64 %a) {
207+
; RV32I-LABEL: sexti32_i64:
208+
; RV32I: # %bb.0:
209+
; RV32I-NEXT: srai a1, a0, 31
210+
; RV32I-NEXT: ret
211+
;
212+
; RV32XQCIBM-LABEL: sexti32_i64:
213+
; RV32XQCIBM: # %bb.0:
214+
; RV32XQCIBM-NEXT: srai a1, a0, 31
215+
; RV32XQCIBM-NEXT: ret
216+
%shl = shl i64 %a, 32
217+
%shr = ashr exact i64 %shl, 32
218+
ret i64 %shr
219+
}
220+
221+
define i64 @sexti32_i64_2(i32 %a) {
222+
; RV32I-LABEL: sexti32_i64_2:
223+
; RV32I: # %bb.0:
224+
; RV32I-NEXT: srai a1, a0, 31
225+
; RV32I-NEXT: ret
226+
;
227+
; RV32XQCIBM-LABEL: sexti32_i64_2:
228+
; RV32XQCIBM: # %bb.0:
229+
; RV32XQCIBM-NEXT: srai a1, a0, 31
230+
; RV32XQCIBM-NEXT: ret
231+
%1 = sext i32 %a to i64
232+
ret i64 %1
233+
}

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