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[LoongArch] Merge base and offset for LSX/LASX memory accesses (#104452)
1 parent 371f936 commit 985d64b

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9 files changed

+74
-103
lines changed

9 files changed

+74
-103
lines changed

‎llvm/lib/Target/LoongArch/LoongArchMergeBaseOffset.cpp

Lines changed: 23 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -381,6 +381,14 @@ static unsigned getNewOpc(unsigned Op, bool isLarge) {
381381
return isLarge ? LoongArch::FLDX_S : LoongArch::FLD_S;
382382
case LoongArch::FLD_D:
383383
return isLarge ? LoongArch::FLDX_D : LoongArch::FLD_D;
384+
case LoongArch::VLD:
385+
return isLarge ? LoongArch::VLDX : LoongArch::VLD;
386+
case LoongArch::XVLD:
387+
return isLarge ? LoongArch::XVLDX : LoongArch::XVLD;
388+
case LoongArch::VLDREPL_B:
389+
return LoongArch::VLDREPL_B;
390+
case LoongArch::XVLDREPL_B:
391+
return LoongArch::XVLDREPL_B;
384392
case LoongArch::ST_B:
385393
return isLarge ? LoongArch::STX_B : LoongArch::ST_B;
386394
case LoongArch::ST_H:
@@ -395,6 +403,10 @@ static unsigned getNewOpc(unsigned Op, bool isLarge) {
395403
return isLarge ? LoongArch::FSTX_S : LoongArch::FST_S;
396404
case LoongArch::FST_D:
397405
return isLarge ? LoongArch::FSTX_D : LoongArch::FST_D;
406+
case LoongArch::VST:
407+
return isLarge ? LoongArch::VSTX : LoongArch::VST;
408+
case LoongArch::XVST:
409+
return isLarge ? LoongArch::XVSTX : LoongArch::XVST;
398410
default:
399411
llvm_unreachable("Unexpected opcode for replacement");
400412
}
@@ -444,6 +456,12 @@ bool LoongArchMergeBaseOffsetOpt::foldIntoMemoryOps(MachineInstr &Hi20,
444456
default:
445457
LLVM_DEBUG(dbgs() << "Not a load or store instruction: " << UseMI);
446458
return false;
459+
case LoongArch::VLDREPL_B:
460+
case LoongArch::XVLDREPL_B:
461+
// We can't do this for large pattern.
462+
if (Last)
463+
return false;
464+
[[fallthrough]];
447465
case LoongArch::LD_B:
448466
case LoongArch::LD_H:
449467
case LoongArch::LD_W:
@@ -455,14 +473,18 @@ bool LoongArchMergeBaseOffsetOpt::foldIntoMemoryOps(MachineInstr &Hi20,
455473
case LoongArch::LDPTR_D:
456474
case LoongArch::FLD_S:
457475
case LoongArch::FLD_D:
476+
case LoongArch::VLD:
477+
case LoongArch::XVLD:
458478
case LoongArch::ST_B:
459479
case LoongArch::ST_H:
460480
case LoongArch::ST_W:
461481
case LoongArch::ST_D:
462482
case LoongArch::STPTR_W:
463483
case LoongArch::STPTR_D:
464484
case LoongArch::FST_S:
465-
case LoongArch::FST_D: {
485+
case LoongArch::FST_D:
486+
case LoongArch::VST:
487+
case LoongArch::XVST: {
466488
if (UseMI.getOperand(1).isFI())
467489
return false;
468490
// Register defined by Lo should not be the value register.

‎llvm/test/CodeGen/LoongArch/can-not-realign-stack.ll

Lines changed: 4 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -17,20 +17,16 @@ define dso_local noundef signext i32 @main() nounwind {
1717
; CHECK-NEXT: addi.d $sp, $sp, -272
1818
; CHECK-NEXT: st.d $ra, $sp, 264 # 8-byte Folded Spill
1919
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI0_0)
20-
; CHECK-NEXT: addi.d $a0, $a0, %pc_lo12(.LCPI0_0)
21-
; CHECK-NEXT: xvld $xr0, $a0, 0
20+
; CHECK-NEXT: xvld $xr0, $a0, %pc_lo12(.LCPI0_0)
2221
; CHECK-NEXT: xvst $xr0, $sp, 96 # 32-byte Folded Spill
2322
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI0_1)
24-
; CHECK-NEXT: addi.d $a0, $a0, %pc_lo12(.LCPI0_1)
25-
; CHECK-NEXT: xvld $xr1, $a0, 0
23+
; CHECK-NEXT: xvld $xr1, $a0, %pc_lo12(.LCPI0_1)
2624
; CHECK-NEXT: xvst $xr1, $sp, 64 # 32-byte Folded Spill
2725
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI0_2)
28-
; CHECK-NEXT: addi.d $a0, $a0, %pc_lo12(.LCPI0_2)
29-
; CHECK-NEXT: xvld $xr2, $a0, 0
26+
; CHECK-NEXT: xvld $xr2, $a0, %pc_lo12(.LCPI0_2)
3027
; CHECK-NEXT: xvst $xr2, $sp, 32 # 32-byte Folded Spill
3128
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI0_3)
32-
; CHECK-NEXT: addi.d $a0, $a0, %pc_lo12(.LCPI0_3)
33-
; CHECK-NEXT: xvld $xr3, $a0, 0
29+
; CHECK-NEXT: xvld $xr3, $a0, %pc_lo12(.LCPI0_3)
3430
; CHECK-NEXT: xvst $xr3, $sp, 0 # 32-byte Folded Spill
3531
; CHECK-NEXT: xvst $xr0, $sp, 136
3632
; CHECK-NEXT: xvst $xr1, $sp, 168

‎llvm/test/CodeGen/LoongArch/lasx/build-vector.ll

Lines changed: 6 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -153,8 +153,7 @@ define void @buildvector_v32i8_const(ptr %dst) nounwind {
153153
; CHECK-LABEL: buildvector_v32i8_const:
154154
; CHECK: # %bb.0: # %entry
155155
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI12_0)
156-
; CHECK-NEXT: addi.d $a1, $a1, %pc_lo12(.LCPI12_0)
157-
; CHECK-NEXT: xvld $xr0, $a1, 0
156+
; CHECK-NEXT: xvld $xr0, $a1, %pc_lo12(.LCPI12_0)
158157
; CHECK-NEXT: xvst $xr0, $a0, 0
159158
; CHECK-NEXT: ret
160159
entry:
@@ -166,8 +165,7 @@ define void @buildvector_v16i16_const(ptr %dst) nounwind {
166165
; CHECK-LABEL: buildvector_v16i16_const:
167166
; CHECK: # %bb.0: # %entry
168167
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI13_0)
169-
; CHECK-NEXT: addi.d $a1, $a1, %pc_lo12(.LCPI13_0)
170-
; CHECK-NEXT: xvld $xr0, $a1, 0
168+
; CHECK-NEXT: xvld $xr0, $a1, %pc_lo12(.LCPI13_0)
171169
; CHECK-NEXT: xvst $xr0, $a0, 0
172170
; CHECK-NEXT: ret
173171
entry:
@@ -179,8 +177,7 @@ define void @buildvector_v8i32_const(ptr %dst) nounwind {
179177
; CHECK-LABEL: buildvector_v8i32_const:
180178
; CHECK: # %bb.0: # %entry
181179
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI14_0)
182-
; CHECK-NEXT: addi.d $a1, $a1, %pc_lo12(.LCPI14_0)
183-
; CHECK-NEXT: xvld $xr0, $a1, 0
180+
; CHECK-NEXT: xvld $xr0, $a1, %pc_lo12(.LCPI14_0)
184181
; CHECK-NEXT: xvst $xr0, $a0, 0
185182
; CHECK-NEXT: ret
186183
entry:
@@ -192,8 +189,7 @@ define void @buildvector_v4i64_const(ptr %dst) nounwind {
192189
; CHECK-LABEL: buildvector_v4i64_const:
193190
; CHECK: # %bb.0: # %entry
194191
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI15_0)
195-
; CHECK-NEXT: addi.d $a1, $a1, %pc_lo12(.LCPI15_0)
196-
; CHECK-NEXT: xvld $xr0, $a1, 0
192+
; CHECK-NEXT: xvld $xr0, $a1, %pc_lo12(.LCPI15_0)
197193
; CHECK-NEXT: xvst $xr0, $a0, 0
198194
; CHECK-NEXT: ret
199195
entry:
@@ -205,8 +201,7 @@ define void @buildvector_v2f32_const(ptr %dst) nounwind {
205201
; CHECK-LABEL: buildvector_v2f32_const:
206202
; CHECK: # %bb.0: # %entry
207203
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI16_0)
208-
; CHECK-NEXT: addi.d $a1, $a1, %pc_lo12(.LCPI16_0)
209-
; CHECK-NEXT: xvld $xr0, $a1, 0
204+
; CHECK-NEXT: xvld $xr0, $a1, %pc_lo12(.LCPI16_0)
210205
; CHECK-NEXT: xvst $xr0, $a0, 0
211206
; CHECK-NEXT: ret
212207
entry:
@@ -218,8 +213,7 @@ define void @buildvector_v4f64_const(ptr %dst) nounwind {
218213
; CHECK-LABEL: buildvector_v4f64_const:
219214
; CHECK: # %bb.0: # %entry
220215
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI17_0)
221-
; CHECK-NEXT: addi.d $a1, $a1, %pc_lo12(.LCPI17_0)
222-
; CHECK-NEXT: xvld $xr0, $a1, 0
216+
; CHECK-NEXT: xvld $xr0, $a1, %pc_lo12(.LCPI17_0)
223217
; CHECK-NEXT: xvst $xr0, $a0, 0
224218
; CHECK-NEXT: ret
225219
entry:

‎llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvshuf.ll

Lines changed: 5 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -6,8 +6,7 @@ define <32 x i8> @shufflevector_v32i8(<32 x i8> %a, <32 x i8> %b) {
66
; CHECK-LABEL: shufflevector_v32i8:
77
; CHECK: # %bb.0:
88
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI0_0)
9-
; CHECK-NEXT: addi.d $a0, $a0, %pc_lo12(.LCPI0_0)
10-
; CHECK-NEXT: xvld $xr2, $a0, 0
9+
; CHECK-NEXT: xvld $xr2, $a0, %pc_lo12(.LCPI0_0)
1110
; CHECK-NEXT: xvshuf.b $xr0, $xr1, $xr0, $xr2
1211
; CHECK-NEXT: ret
1312
%c = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 1, i32 3, i32 5, i32 7, i32 8, i32 10, i32 12, i32 15, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39,
@@ -20,8 +19,7 @@ define <16 x i16> @shufflevector_v16i16(<16 x i16> %a, <16 x i16> %b) {
2019
; CHECK-LABEL: shufflevector_v16i16:
2120
; CHECK: # %bb.0:
2221
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI1_0)
23-
; CHECK-NEXT: addi.d $a0, $a0, %pc_lo12(.LCPI1_0)
24-
; CHECK-NEXT: xvld $xr2, $a0, 0
22+
; CHECK-NEXT: xvld $xr2, $a0, %pc_lo12(.LCPI1_0)
2523
; CHECK-NEXT: xvpermi.d $xr0, $xr0, 78
2624
; CHECK-NEXT: xvpermi.d $xr1, $xr1, 78
2725
; CHECK-NEXT: xvshuf.h $xr2, $xr1, $xr0
@@ -37,8 +35,7 @@ define <8 x i32> @shufflevector_v8i32(<8 x i32> %a, <8 x i32> %b) {
3735
; CHECK-LABEL: shufflevector_v8i32:
3836
; CHECK: # %bb.0:
3937
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI2_0)
40-
; CHECK-NEXT: addi.d $a0, $a0, %pc_lo12(.LCPI2_0)
41-
; CHECK-NEXT: xvld $xr2, $a0, 0
38+
; CHECK-NEXT: xvld $xr2, $a0, %pc_lo12(.LCPI2_0)
4239
; CHECK-NEXT: xvpermi.d $xr0, $xr0, 68
4340
; CHECK-NEXT: xvpermi.d $xr1, $xr1, 68
4441
; CHECK-NEXT: xvshuf.w $xr2, $xr1, $xr0
@@ -53,8 +50,7 @@ define <4 x i64> @shufflevector_v4i64(<4 x i64> %a, <4 x i64> %b) {
5350
; CHECK-LABEL: shufflevector_v4i64:
5451
; CHECK: # %bb.0:
5552
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_0)
56-
; CHECK-NEXT: addi.d $a0, $a0, %pc_lo12(.LCPI3_0)
57-
; CHECK-NEXT: xvld $xr2, $a0, 0
53+
; CHECK-NEXT: xvld $xr2, $a0, %pc_lo12(.LCPI3_0)
5854
; CHECK-NEXT: xvpermi.d $xr0, $xr0, 238
5955
; CHECK-NEXT: xvpermi.d $xr1, $xr1, 238
6056
; CHECK-NEXT: xvshuf.d $xr2, $xr1, $xr0
@@ -69,8 +65,7 @@ define <8 x float> @shufflevector_v8f32(<8 x float> %a, <8 x float> %b) {
6965
; CHECK-LABEL: shufflevector_v8f32:
7066
; CHECK: # %bb.0:
7167
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI4_0)
72-
; CHECK-NEXT: addi.d $a0, $a0, %pc_lo12(.LCPI4_0)
73-
; CHECK-NEXT: xvld $xr2, $a0, 0
68+
; CHECK-NEXT: xvld $xr2, $a0, %pc_lo12(.LCPI4_0)
7469
; CHECK-NEXT: xvshuf.w $xr2, $xr1, $xr0
7570
; CHECK-NEXT: xvori.b $xr0, $xr2, 0
7671
; CHECK-NEXT: ret

‎llvm/test/CodeGen/LoongArch/lasx/vselect.ll

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -72,8 +72,7 @@ define void @select_v4i64(ptr %res, ptr %a0, ptr %a1) nounwind {
7272
; CHECK-NEXT: xvld $xr0, $a1, 0
7373
; CHECK-NEXT: xvld $xr1, $a2, 0
7474
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI4_0)
75-
; CHECK-NEXT: addi.d $a1, $a1, %pc_lo12(.LCPI4_0)
76-
; CHECK-NEXT: xvld $xr2, $a1, 0
75+
; CHECK-NEXT: xvld $xr2, $a1, %pc_lo12(.LCPI4_0)
7776
; CHECK-NEXT: xvbitsel.v $xr0, $xr1, $xr0, $xr2
7877
; CHECK-NEXT: xvst $xr0, $a0, 0
7978
; CHECK-NEXT: ret

‎llvm/test/CodeGen/LoongArch/lsx/build-vector.ll

Lines changed: 6 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -153,8 +153,7 @@ define void @buildvector_v16i8_const(ptr %dst) nounwind {
153153
; CHECK-LABEL: buildvector_v16i8_const:
154154
; CHECK: # %bb.0: # %entry
155155
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI12_0)
156-
; CHECK-NEXT: addi.d $a1, $a1, %pc_lo12(.LCPI12_0)
157-
; CHECK-NEXT: vld $vr0, $a1, 0
156+
; CHECK-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI12_0)
158157
; CHECK-NEXT: vst $vr0, $a0, 0
159158
; CHECK-NEXT: ret
160159
entry:
@@ -166,8 +165,7 @@ define void @buildvector_v8i16_const(ptr %dst) nounwind {
166165
; CHECK-LABEL: buildvector_v8i16_const:
167166
; CHECK: # %bb.0: # %entry
168167
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI13_0)
169-
; CHECK-NEXT: addi.d $a1, $a1, %pc_lo12(.LCPI13_0)
170-
; CHECK-NEXT: vld $vr0, $a1, 0
168+
; CHECK-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI13_0)
171169
; CHECK-NEXT: vst $vr0, $a0, 0
172170
; CHECK-NEXT: ret
173171
entry:
@@ -179,8 +177,7 @@ define void @buildvector_v4i32_const(ptr %dst) nounwind {
179177
; CHECK-LABEL: buildvector_v4i32_const:
180178
; CHECK: # %bb.0: # %entry
181179
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI14_0)
182-
; CHECK-NEXT: addi.d $a1, $a1, %pc_lo12(.LCPI14_0)
183-
; CHECK-NEXT: vld $vr0, $a1, 0
180+
; CHECK-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI14_0)
184181
; CHECK-NEXT: vst $vr0, $a0, 0
185182
; CHECK-NEXT: ret
186183
entry:
@@ -192,8 +189,7 @@ define void @buildvector_v2i64_const(ptr %dst) nounwind {
192189
; CHECK-LABEL: buildvector_v2i64_const:
193190
; CHECK: # %bb.0: # %entry
194191
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI15_0)
195-
; CHECK-NEXT: addi.d $a1, $a1, %pc_lo12(.LCPI15_0)
196-
; CHECK-NEXT: vld $vr0, $a1, 0
192+
; CHECK-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI15_0)
197193
; CHECK-NEXT: vst $vr0, $a0, 0
198194
; CHECK-NEXT: ret
199195
entry:
@@ -205,8 +201,7 @@ define void @buildvector_v2f32_const(ptr %dst) nounwind {
205201
; CHECK-LABEL: buildvector_v2f32_const:
206202
; CHECK: # %bb.0: # %entry
207203
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI16_0)
208-
; CHECK-NEXT: addi.d $a1, $a1, %pc_lo12(.LCPI16_0)
209-
; CHECK-NEXT: vld $vr0, $a1, 0
204+
; CHECK-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI16_0)
210205
; CHECK-NEXT: vst $vr0, $a0, 0
211206
; CHECK-NEXT: ret
212207
entry:
@@ -218,8 +213,7 @@ define void @buildvector_v2f64_const(ptr %dst) nounwind {
218213
; CHECK-LABEL: buildvector_v2f64_const:
219214
; CHECK: # %bb.0: # %entry
220215
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI17_0)
221-
; CHECK-NEXT: addi.d $a1, $a1, %pc_lo12(.LCPI17_0)
222-
; CHECK-NEXT: vld $vr0, $a1, 0
216+
; CHECK-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI17_0)
223217
; CHECK-NEXT: vst $vr0, $a0, 0
224218
; CHECK-NEXT: ret
225219
entry:

‎llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vshuf.ll

Lines changed: 6 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -5,8 +5,7 @@ define <16 x i8> @shufflevector_v16i8(<16 x i8> %a, <16 x i8> %b) {
55
; CHECK-LABEL: shufflevector_v16i8:
66
; CHECK: # %bb.0:
77
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI0_0)
8-
; CHECK-NEXT: addi.d $a0, $a0, %pc_lo12(.LCPI0_0)
9-
; CHECK-NEXT: vld $vr2, $a0, 0
8+
; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI0_0)
109
; CHECK-NEXT: vshuf.b $vr0, $vr1, $vr0, $vr2
1110
; CHECK-NEXT: ret
1211
%c = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 8, i32 10, i32 12, i32 15, i32 2, i32 4, i32 6, i32 8, i32 25, i32 30, i32 31, i32 31>
@@ -18,8 +17,7 @@ define <8 x i16> @shufflevector_v8i16(<8 x i16> %a, <8 x i16> %b) {
1817
; CHECK-LABEL: shufflevector_v8i16:
1918
; CHECK: # %bb.0:
2019
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI1_0)
21-
; CHECK-NEXT: addi.d $a0, $a0, %pc_lo12(.LCPI1_0)
22-
; CHECK-NEXT: vld $vr2, $a0, 0
20+
; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI1_0)
2321
; CHECK-NEXT: vshuf.h $vr2, $vr1, $vr0
2422
; CHECK-NEXT: vori.b $vr0, $vr2, 0
2523
; CHECK-NEXT: ret
@@ -32,8 +30,7 @@ define <4 x i32> @shufflevector_v4i32(<4 x i32> %a, <4 x i32> %b) {
3230
; CHECK-LABEL: shufflevector_v4i32:
3331
; CHECK: # %bb.0:
3432
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI2_0)
35-
; CHECK-NEXT: addi.d $a0, $a0, %pc_lo12(.LCPI2_0)
36-
; CHECK-NEXT: vld $vr2, $a0, 0
33+
; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI2_0)
3734
; CHECK-NEXT: vshuf.w $vr2, $vr1, $vr0
3835
; CHECK-NEXT: vori.b $vr0, $vr2, 0
3936
; CHECK-NEXT: ret
@@ -46,8 +43,7 @@ define <2 x i64> @shufflevector_v2i64(<2 x i64> %a, <2 x i64> %b) {
4643
; CHECK-LABEL: shufflevector_v2i64:
4744
; CHECK: # %bb.0:
4845
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_0)
49-
; CHECK-NEXT: addi.d $a0, $a0, %pc_lo12(.LCPI3_0)
50-
; CHECK-NEXT: vld $vr2, $a0, 0
46+
; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI3_0)
5147
; CHECK-NEXT: vshuf.d $vr2, $vr1, $vr0
5248
; CHECK-NEXT: vori.b $vr0, $vr2, 0
5349
; CHECK-NEXT: ret
@@ -60,8 +56,7 @@ define <4 x float> @shufflevector_v4f32(<4 x float> %a, <4 x float> %b) {
6056
; CHECK-LABEL: shufflevector_v4f32:
6157
; CHECK: # %bb.0:
6258
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI4_0)
63-
; CHECK-NEXT: addi.d $a0, $a0, %pc_lo12(.LCPI4_0)
64-
; CHECK-NEXT: vld $vr2, $a0, 0
59+
; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI4_0)
6560
; CHECK-NEXT: vshuf.w $vr2, $vr1, $vr0
6661
; CHECK-NEXT: vori.b $vr0, $vr2, 0
6762
; CHECK-NEXT: ret
@@ -74,8 +69,7 @@ define <2 x double> @shufflevector_v2f64(<2 x double> %a, <2 x double> %b) {
7469
; CHECK-LABEL: shufflevector_v2f64:
7570
; CHECK: # %bb.0:
7671
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI5_0)
77-
; CHECK-NEXT: addi.d $a0, $a0, %pc_lo12(.LCPI5_0)
78-
; CHECK-NEXT: vld $vr2, $a0, 0
72+
; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI5_0)
7973
; CHECK-NEXT: vshuf.d $vr2, $vr1, $vr0
8074
; CHECK-NEXT: vori.b $vr0, $vr2, 0
8175
; CHECK-NEXT: ret

‎llvm/test/CodeGen/LoongArch/lsx/vselect.ll

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -72,8 +72,7 @@ define void @select_v2i64(ptr %res, ptr %a0, ptr %a1) nounwind {
7272
; CHECK-NEXT: vld $vr0, $a1, 0
7373
; CHECK-NEXT: vld $vr1, $a2, 0
7474
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI4_0)
75-
; CHECK-NEXT: addi.d $a1, $a1, %pc_lo12(.LCPI4_0)
76-
; CHECK-NEXT: vld $vr2, $a1, 0
75+
; CHECK-NEXT: vld $vr2, $a1, %pc_lo12(.LCPI4_0)
7776
; CHECK-NEXT: vbitsel.v $vr0, $vr1, $vr0, $vr2
7877
; CHECK-NEXT: vst $vr0, $a0, 0
7978
; CHECK-NEXT: ret

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