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[RISCV] Remove many ImmType parameters from tablegen classes. NFC
These usually have a single value that is always used. We can just hardcode into the class body.
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-35
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2 files changed

+31
-35
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‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Lines changed: 29 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -2317,11 +2317,11 @@ multiclass VPseudoVSLD1_VF<string Constraint = ""> {
23172317
}
23182318
}
23192319

2320-
multiclass VPseudoBinaryV_VI<Operand ImmType = simm5, LMULInfo m, string Constraint = ""> {
2320+
multiclass VPseudoBinaryV_VI<Operand ImmType, LMULInfo m, string Constraint = ""> {
23212321
defm _VI : VPseudoBinary<m.vrclass, m.vrclass, ImmType, m, Constraint>;
23222322
}
23232323

2324-
multiclass VPseudoBinaryV_VI_RM<Operand ImmType = simm5, LMULInfo m, string Constraint = ""> {
2324+
multiclass VPseudoBinaryV_VI_RM<Operand ImmType, LMULInfo m, string Constraint = ""> {
23252325
defm _VI : VPseudoBinaryRoundingMode<m.vrclass, m.vrclass, ImmType, m, Constraint>;
23262326
}
23272327

@@ -2696,13 +2696,13 @@ multiclass VPseudoBinaryM_VI<LMULInfo m, int TargetConstraintType = 1> {
26962696
!if(!ge(m.octuple, 16), "@earlyclobber $rd", ""), TargetConstraintType>;
26972697
}
26982698

2699-
multiclass VPseudoVGTR_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
2699+
multiclass VPseudoVGTR_VV_VX_VI<string Constraint = ""> {
27002700
foreach m = MxList in {
27012701
defvar mx = m.MX;
27022702
defm "" : VPseudoBinaryV_VX<m, Constraint>,
27032703
SchedBinary<"WriteVRGatherVX", "ReadVRGatherVX_data",
27042704
"ReadVRGatherVX_index", mx, forceMergeOpRead=true>;
2705-
defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>,
2705+
defm "" : VPseudoBinaryV_VI<uimm5, m, Constraint>,
27062706
SchedUnary<"WriteVRGatherVI", "ReadVRGatherVI_data", mx,
27072707
forceMergeOpRead=true>;
27082708

@@ -2715,8 +2715,7 @@ multiclass VPseudoVGTR_VV_VX_VI<Operand ImmType = simm5, string Constraint = "">
27152715
}
27162716
}
27172717

2718-
multiclass VPseudoVSALU_VV_VX_VI<Operand ImmType = simm5, string Constraint = "",
2719-
bit Commutable = 0> {
2718+
multiclass VPseudoVSALU_VV_VX_VI<string Constraint = "", bit Commutable = 0> {
27202719
foreach m = MxList in {
27212720
defvar mx = m.MX;
27222721
defm "" : VPseudoBinaryV_VV<m, Constraint, Commutable=Commutable>,
@@ -2725,13 +2724,13 @@ multiclass VPseudoVSALU_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""
27252724
defm "" : VPseudoBinaryV_VX<m, Constraint>,
27262725
SchedBinary<"WriteVSALUX", "ReadVSALUV", "ReadVSALUX", mx,
27272726
forceMergeOpRead=true>;
2728-
defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>,
2727+
defm "" : VPseudoBinaryV_VI<simm5, m, Constraint>,
27292728
SchedUnary<"WriteVSALUI", "ReadVSALUV", mx, forceMergeOpRead=true>;
27302729
}
27312730
}
27322731

27332732

2734-
multiclass VPseudoVSHT_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
2733+
multiclass VPseudoVSHT_VV_VX_VI<string Constraint = ""> {
27352734
foreach m = MxList in {
27362735
defvar mx = m.MX;
27372736
defm "" : VPseudoBinaryV_VV<m, Constraint>,
@@ -2740,12 +2739,12 @@ multiclass VPseudoVSHT_VV_VX_VI<Operand ImmType = simm5, string Constraint = "">
27402739
defm "" : VPseudoBinaryV_VX<m, Constraint>,
27412740
SchedBinary<"WriteVShiftX", "ReadVShiftV", "ReadVShiftX", mx,
27422741
forceMergeOpRead=true>;
2743-
defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>,
2742+
defm "" : VPseudoBinaryV_VI<uimm5, m, Constraint>,
27442743
SchedUnary<"WriteVShiftI", "ReadVShiftV", mx, forceMergeOpRead=true>;
27452744
}
27462745
}
27472746

2748-
multiclass VPseudoVSSHT_VV_VX_VI_RM<Operand ImmType = simm5, string Constraint = ""> {
2747+
multiclass VPseudoVSSHT_VV_VX_VI_RM<string Constraint = ""> {
27492748
foreach m = MxList in {
27502749
defvar mx = m.MX;
27512750
defm "" : VPseudoBinaryV_VV_RM<m, Constraint>,
@@ -2754,13 +2753,12 @@ multiclass VPseudoVSSHT_VV_VX_VI_RM<Operand ImmType = simm5, string Constraint =
27542753
defm "" : VPseudoBinaryV_VX_RM<m, Constraint>,
27552754
SchedBinary<"WriteVSShiftX", "ReadVSShiftV", "ReadVSShiftX", mx,
27562755
forceMergeOpRead=true>;
2757-
defm "" : VPseudoBinaryV_VI_RM<ImmType, m, Constraint>,
2756+
defm "" : VPseudoBinaryV_VI_RM<uimm5, m, Constraint>,
27582757
SchedUnary<"WriteVSShiftI", "ReadVSShiftV", mx, forceMergeOpRead=true>;
27592758
}
27602759
}
27612760

2762-
multiclass VPseudoVALU_VV_VX_VI<Operand ImmType = simm5, string Constraint = "",
2763-
bit Commutable = 0> {
2761+
multiclass VPseudoVALU_VV_VX_VI<string Constraint = "", bit Commutable = 0> {
27642762
foreach m = MxList in {
27652763
defvar mx = m.MX;
27662764
defm "" : VPseudoBinaryV_VV<m, Constraint, Commutable=Commutable>,
@@ -2769,7 +2767,7 @@ multiclass VPseudoVALU_VV_VX_VI<Operand ImmType = simm5, string Constraint = "",
27692767
defm "" : VPseudoBinaryV_VX<m, Constraint>,
27702768
SchedBinary<"WriteVIALUX", "ReadVIALUV", "ReadVIALUX", mx,
27712769
forceMergeOpRead=true>;
2772-
defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>,
2770+
defm "" : VPseudoBinaryV_VI<simm5, m, Constraint>,
27732771
SchedUnary<"WriteVIALUI", "ReadVIALUV", mx, forceMergeOpRead=true>;
27742772
}
27752773
}
@@ -2962,13 +2960,13 @@ multiclass VPseudoVALU_VF_RM {
29622960
}
29632961
}
29642962

2965-
multiclass VPseudoVALU_VX_VI<Operand ImmType = simm5> {
2963+
multiclass VPseudoVALU_VX_VI {
29662964
foreach m = MxList in {
29672965
defvar mx = m.MX;
29682966
defm "" : VPseudoBinaryV_VX<m>,
29692967
SchedBinary<"WriteVIALUX", "ReadVIALUV", "ReadVIALUX", mx,
29702968
forceMergeOpRead=true>;
2971-
defm "" : VPseudoBinaryV_VI<ImmType, m>,
2969+
defm "" : VPseudoBinaryV_VI<simm5, m>,
29722970
SchedUnary<"WriteVIALUI", "ReadVIALUV", mx, forceMergeOpRead=true>;
29732971
}
29742972
}
@@ -3333,8 +3331,8 @@ multiclass VPseudoVSLDV_VX<LMULInfo m, string Constraint = ""> {
33333331
defm _VX : VPseudoVSLDVWithPolicy<m.vrclass, m.vrclass, GPR, m, Constraint>;
33343332
}
33353333

3336-
multiclass VPseudoVSLDV_VI<Operand ImmType = simm5, LMULInfo m, string Constraint = ""> {
3337-
defm _VI : VPseudoVSLDVWithPolicy<m.vrclass, m.vrclass, ImmType, m, Constraint>;
3334+
multiclass VPseudoVSLDV_VI<LMULInfo m, string Constraint = ""> {
3335+
defm _VI : VPseudoVSLDVWithPolicy<m.vrclass, m.vrclass, uimm5, m, Constraint>;
33383336
}
33393337

33403338
multiclass VPseudoVMAC_VV_VX_AAXA<string Constraint = ""> {
@@ -3366,15 +3364,14 @@ multiclass VPseudoVMAC_VV_VF_AAXA_RM<string Constraint = ""> {
33663364
}
33673365
}
33683366

3369-
multiclass VPseudoVSLD_VX_VI<Operand ImmType = simm5, bit slidesUp = false,
3370-
string Constraint = ""> {
3367+
multiclass VPseudoVSLD_VX_VI<bit slidesUp = false, string Constraint = ""> {
33713368
defvar WriteSlideX = !if(slidesUp, "WriteVSlideUpX", "WriteVSlideDownX");
33723369
foreach m = MxList in {
33733370
defvar mx = m.MX;
33743371
defm "" : VPseudoVSLDV_VX<m, Constraint>,
33753372
SchedTernary<WriteSlideX, "ReadVISlideV", "ReadVISlideV",
33763373
"ReadVISlideX", mx>;
3377-
defm "" : VPseudoVSLDV_VI<ImmType, m, Constraint>,
3374+
defm "" : VPseudoVSLDV_VI<m, Constraint>,
33783375
SchedBinary<"WriteVSlideI", "ReadVISlideV", "ReadVISlideV", mx>;
33793376
}
33803377
}
@@ -5441,7 +5438,7 @@ multiclass VPatBinaryV_VV_VX_VI<string intrinsic, string instruction,
54415438
VPatBinaryV_VI<intrinsic, instruction, vtilist, ImmType>;
54425439

54435440
multiclass VPatBinaryV_VV_VX_VI_RM<string intrinsic, string instruction,
5444-
list<VTypeInfo> vtilist, Operand ImmType = simm5>
5441+
list<VTypeInfo> vtilist, Operand ImmType>
54455442
: VPatBinaryV_VV_RM<intrinsic, instruction, vtilist>,
54465443
VPatBinaryV_VX_RM<intrinsic, instruction, vtilist>,
54475444
VPatBinaryV_VI_RM<intrinsic, instruction, vtilist, ImmType>;
@@ -5777,7 +5774,7 @@ multiclass VPatTernaryV_VV_VX_AAXA_RM<string intrinsic, string instruction,
57775774
VPatTernaryV_VX_AAXA_RM<intrinsic, instruction, vtilist, isSEWAware>;
57785775

57795776
multiclass VPatTernaryV_VX_VI<string intrinsic, string instruction,
5780-
list<VTypeInfo> vtilist, Operand Imm_type = simm5>
5777+
list<VTypeInfo> vtilist, Operand Imm_type>
57815778
: VPatTernaryV_VX<intrinsic, instruction, vtilist>,
57825779
VPatTernaryV_VI<intrinsic, instruction, vtilist, Imm_type>;
57835780

@@ -5809,7 +5806,7 @@ multiclass VPatBinaryM_VX_VI<string intrinsic, string instruction,
58095806
VPatBinaryM_VI<intrinsic, instruction, vtilist>;
58105807

58115808
multiclass VPatBinaryV_VV_VX_VI_INT<string intrinsic, string instruction,
5812-
list<VTypeInfo> vtilist, Operand ImmType = simm5>
5809+
list<VTypeInfo> vtilist, Operand ImmType>
58135810
: VPatBinaryV_VV_INT<intrinsic#"_vv", instruction, vtilist>,
58145811
VPatBinaryV_VX_INT<intrinsic#"_vx", instruction, vtilist>,
58155812
VPatBinaryV_VI<intrinsic#"_vx", instruction, vtilist, ImmType>;
@@ -6329,9 +6326,9 @@ defm PseudoVXOR : VPseudoVALU_VV_VX_VI<Commutable=1>;
63296326
//===----------------------------------------------------------------------===//
63306327
// 11.6. Vector Single-Width Bit Shift Instructions
63316328
//===----------------------------------------------------------------------===//
6332-
defm PseudoVSLL : VPseudoVSHT_VV_VX_VI<uimm5>;
6333-
defm PseudoVSRL : VPseudoVSHT_VV_VX_VI<uimm5>;
6334-
defm PseudoVSRA : VPseudoVSHT_VV_VX_VI<uimm5>;
6329+
defm PseudoVSLL : VPseudoVSHT_VV_VX_VI;
6330+
defm PseudoVSRL : VPseudoVSHT_VV_VX_VI;
6331+
defm PseudoVSRA : VPseudoVSHT_VV_VX_VI;
63356332

63366333
//===----------------------------------------------------------------------===//
63376334
// 11.7. Vector Narrowing Integer Right Shift Instructions
@@ -6440,8 +6437,8 @@ let Defs = [VXSAT] in {
64406437
//===----------------------------------------------------------------------===//
64416438
// 12.4. Vector Single-Width Scaling Shift Instructions
64426439
//===----------------------------------------------------------------------===//
6443-
defm PseudoVSSRL : VPseudoVSSHT_VV_VX_VI_RM<uimm5>;
6444-
defm PseudoVSSRA : VPseudoVSSHT_VV_VX_VI_RM<uimm5>;
6440+
defm PseudoVSSRL : VPseudoVSSHT_VV_VX_VI_RM;
6441+
defm PseudoVSSRA : VPseudoVSSHT_VV_VX_VI_RM;
64456442

64466443
//===----------------------------------------------------------------------===//
64476444
// 12.5. Vector Narrowing Fixed-Point Clip Instructions
@@ -6826,8 +6823,8 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
68266823
// 16.3. Vector Slide Instructions
68276824
//===----------------------------------------------------------------------===//
68286825
let Predicates = [HasVInstructions] in {
6829-
defm PseudoVSLIDEUP : VPseudoVSLD_VX_VI<uimm5, /*slidesUp=*/true, "@earlyclobber $rd">;
6830-
defm PseudoVSLIDEDOWN : VPseudoVSLD_VX_VI<uimm5, /*slidesUp=*/false>;
6826+
defm PseudoVSLIDEUP : VPseudoVSLD_VX_VI</*slidesUp=*/true, "@earlyclobber $rd">;
6827+
defm PseudoVSLIDEDOWN : VPseudoVSLD_VX_VI</*slidesUp=*/false>;
68316828
defm PseudoVSLIDE1UP : VPseudoVSLD1_VX<"@earlyclobber $rd">;
68326829
defm PseudoVSLIDE1DOWN : VPseudoVSLD1_VX;
68336830
} // Predicates = [HasVInstructions]
@@ -6841,7 +6838,7 @@ let Predicates = [HasVInstructionsAnyF] in {
68416838
// 16.4. Vector Register Gather Instructions
68426839
//===----------------------------------------------------------------------===//
68436840
let Predicates = [HasVInstructions] in {
6844-
defm PseudoVRGATHER : VPseudoVGTR_VV_VX_VI<uimm5, "@earlyclobber $rd">;
6841+
defm PseudoVRGATHER : VPseudoVGTR_VV_VX_VI<"@earlyclobber $rd">;
68456842
defm PseudoVRGATHEREI16 : VPseudoVGTR_EI16_VV<Constraint = "@earlyclobber $rd">;
68466843

68476844
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1025,11 +1025,10 @@ multiclass VPatBinaryV_VV_VX_VROL<string intrinsic, string instruction,
10251025
VPatBinaryV_VI_VROL<intrinsic, instruction2, vtilist>;
10261026

10271027
multiclass VPatBinaryV_VV_VX_VI_VROR<string intrinsic, string instruction,
1028-
list<VTypeInfo> vtilist,
1029-
Operand ImmType = uimm6>
1028+
list<VTypeInfo> vtilist>
10301029
: VPatBinaryV_VV<intrinsic, instruction, vtilist>,
10311030
VPatBinaryV_VX_VROTATE<intrinsic, instruction, vtilist>,
1032-
VPatBinaryV_VI<intrinsic, instruction, vtilist, ImmType>;
1031+
VPatBinaryV_VI<intrinsic, instruction, vtilist, uimm6>;
10331032

10341033
multiclass VPatBinaryW_VV_VX_VI_VWSLL<string intrinsic, string instruction,
10351034
list<VTypeInfoToWide> vtilist>

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