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[LoongArch] Pre-commit tests for vector sext & zext (#128835)
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‎llvm/test/CodeGen/LoongArch/lsx/vec-sext.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc --mtriple=loongarch64 --mattr=+lsx %s -o - | FileCheck %s
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define void @load_sext_2i8_to_2i64(ptr %ptr, ptr %dst) {
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; CHECK-LABEL: load_sext_2i8_to_2i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: ld.b $a2, $a0, 0
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; CHECK-NEXT: ld.b $a0, $a0, 1
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; CHECK-NEXT: vinsgr2vr.d $vr0, $a2, 0
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; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 1
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; CHECK-NEXT: vst $vr0, $a1, 0
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; CHECK-NEXT: ret
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entry:
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%A = load <2 x i8>, ptr %ptr
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%B = sext <2 x i8> %A to <2 x i64>
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store <2 x i64> %B, ptr %dst
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ret void
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}
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define void @load_sext_4i8_to_4i32(ptr %ptr, ptr %dst) {
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; CHECK-LABEL: load_sext_4i8_to_4i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: ld.b $a2, $a0, 0
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; CHECK-NEXT: ld.b $a3, $a0, 1
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; CHECK-NEXT: ld.b $a4, $a0, 2
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; CHECK-NEXT: ld.b $a0, $a0, 3
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; CHECK-NEXT: vinsgr2vr.w $vr0, $a2, 0
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; CHECK-NEXT: vinsgr2vr.w $vr0, $a3, 1
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; CHECK-NEXT: vinsgr2vr.w $vr0, $a4, 2
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; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 3
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; CHECK-NEXT: vst $vr0, $a1, 0
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; CHECK-NEXT: ret
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entry:
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%A = load <4 x i8>, ptr %ptr
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%B = sext <4 x i8> %A to <4 x i32>
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store <4 x i32> %B, ptr %dst
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ret void
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}
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define void @load_sext_8i8_to_8i16(ptr %ptr, ptr %dst) {
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; CHECK-LABEL: load_sext_8i8_to_8i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: ld.b $a2, $a0, 0
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; CHECK-NEXT: ld.b $a3, $a0, 1
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; CHECK-NEXT: ld.b $a4, $a0, 2
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; CHECK-NEXT: ld.b $a5, $a0, 3
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; CHECK-NEXT: vinsgr2vr.h $vr0, $a2, 0
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; CHECK-NEXT: vinsgr2vr.h $vr0, $a3, 1
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; CHECK-NEXT: vinsgr2vr.h $vr0, $a4, 2
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; CHECK-NEXT: vinsgr2vr.h $vr0, $a5, 3
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; CHECK-NEXT: ld.b $a2, $a0, 4
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; CHECK-NEXT: ld.b $a3, $a0, 5
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; CHECK-NEXT: ld.b $a4, $a0, 6
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; CHECK-NEXT: ld.b $a0, $a0, 7
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; CHECK-NEXT: vinsgr2vr.h $vr0, $a2, 4
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; CHECK-NEXT: vinsgr2vr.h $vr0, $a3, 5
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; CHECK-NEXT: vinsgr2vr.h $vr0, $a4, 6
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; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 7
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; CHECK-NEXT: vst $vr0, $a1, 0
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; CHECK-NEXT: ret
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entry:
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%A = load <8 x i8>, ptr %ptr
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%B = sext <8 x i8> %A to <8 x i16>
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store <8 x i16> %B, ptr %dst
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ret void
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}
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define void @load_sext_2i16_to_2i64(ptr %ptr, ptr %dst) {
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; CHECK-LABEL: load_sext_2i16_to_2i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: ld.h $a2, $a0, 0
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; CHECK-NEXT: ld.h $a0, $a0, 2
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; CHECK-NEXT: vinsgr2vr.d $vr0, $a2, 0
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; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 1
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; CHECK-NEXT: vst $vr0, $a1, 0
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; CHECK-NEXT: ret
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entry:
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%A = load <2 x i16>, ptr %ptr
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%B = sext <2 x i16> %A to <2 x i64>
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store <2 x i64> %B, ptr %dst
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ret void
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}
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define void @load_sext_4i16_to_4i32(ptr %ptr, ptr %dst) {
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; CHECK-LABEL: load_sext_4i16_to_4i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: ld.h $a2, $a0, 0
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; CHECK-NEXT: ld.h $a3, $a0, 2
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; CHECK-NEXT: ld.h $a4, $a0, 4
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; CHECK-NEXT: ld.h $a0, $a0, 6
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; CHECK-NEXT: vinsgr2vr.w $vr0, $a2, 0
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; CHECK-NEXT: vinsgr2vr.w $vr0, $a3, 1
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; CHECK-NEXT: vinsgr2vr.w $vr0, $a4, 2
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; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 3
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; CHECK-NEXT: vst $vr0, $a1, 0
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; CHECK-NEXT: ret
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entry:
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%A = load <4 x i16>, ptr %ptr
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%B = sext <4 x i16> %A to <4 x i32>
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store <4 x i32> %B, ptr %dst
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ret void
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}
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define void @load_sext_2i32_to_2i64(ptr %ptr, ptr %dst) {
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; CHECK-LABEL: load_sext_2i32_to_2i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: ld.w $a2, $a0, 0
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; CHECK-NEXT: ld.w $a0, $a0, 4
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; CHECK-NEXT: vinsgr2vr.d $vr0, $a2, 0
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; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 1
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; CHECK-NEXT: vst $vr0, $a1, 0
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; CHECK-NEXT: ret
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entry:
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%A = load <2 x i32>, ptr %ptr
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%B = sext <2 x i32> %A to <2 x i64>
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store <2 x i64> %B, ptr %dst
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ret void
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}
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define void @load_sext_16i8_to_16i16(ptr %ptr, ptr %dst) {
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; CHECK-LABEL: load_sext_16i8_to_16i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a0, 0
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0
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; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 0
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
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; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 1
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 2
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; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 2
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 3
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; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 3
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 4
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; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 4
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 5
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; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 5
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 6
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; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 6
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 7
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; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 7
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; CHECK-NEXT: vslli.h $vr1, $vr1, 8
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; CHECK-NEXT: vsrai.h $vr1, $vr1, 8
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 8
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; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 0
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 9
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; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 1
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 10
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; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 2
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 11
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; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 3
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 12
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; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 4
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 13
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; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 5
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 14
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; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 6
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 15
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; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 7
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; CHECK-NEXT: vslli.h $vr0, $vr2, 8
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; CHECK-NEXT: vsrai.h $vr0, $vr0, 8
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; CHECK-NEXT: vst $vr0, $a1, 16
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; CHECK-NEXT: vst $vr1, $a1, 0
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; CHECK-NEXT: ret
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entry:
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%A = load <16 x i8>, ptr %ptr
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%B = sext <16 x i8> %A to <16 x i16>
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store <16 x i16> %B, ptr %dst
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ret void
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}
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define void @load_sext_16i8_to_16i32(ptr %ptr, ptr %dst) {
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; CHECK-LABEL: load_sext_16i8_to_16i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a0, 0
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0
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; CHECK-NEXT: vinsgr2vr.w $vr1, $a0, 0
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
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; CHECK-NEXT: vinsgr2vr.w $vr1, $a0, 1
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 2
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; CHECK-NEXT: vinsgr2vr.w $vr1, $a0, 2
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 3
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; CHECK-NEXT: vinsgr2vr.w $vr1, $a0, 3
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; CHECK-NEXT: vslli.w $vr1, $vr1, 24
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; CHECK-NEXT: vsrai.w $vr1, $vr1, 24
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 4
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; CHECK-NEXT: vinsgr2vr.w $vr2, $a0, 0
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 5
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; CHECK-NEXT: vinsgr2vr.w $vr2, $a0, 1
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 6
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; CHECK-NEXT: vinsgr2vr.w $vr2, $a0, 2
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 7
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; CHECK-NEXT: vinsgr2vr.w $vr2, $a0, 3
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; CHECK-NEXT: vslli.w $vr2, $vr2, 24
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; CHECK-NEXT: vsrai.w $vr2, $vr2, 24
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 8
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; CHECK-NEXT: vinsgr2vr.w $vr3, $a0, 0
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 9
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; CHECK-NEXT: vinsgr2vr.w $vr3, $a0, 1
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 10
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; CHECK-NEXT: vinsgr2vr.w $vr3, $a0, 2
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 11
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; CHECK-NEXT: vinsgr2vr.w $vr3, $a0, 3
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; CHECK-NEXT: vslli.w $vr3, $vr3, 24
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; CHECK-NEXT: vsrai.w $vr3, $vr3, 24
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 12
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; CHECK-NEXT: vinsgr2vr.w $vr4, $a0, 0
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 13
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; CHECK-NEXT: vinsgr2vr.w $vr4, $a0, 1
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 14
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; CHECK-NEXT: vinsgr2vr.w $vr4, $a0, 2
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 15
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; CHECK-NEXT: vinsgr2vr.w $vr4, $a0, 3
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; CHECK-NEXT: vslli.w $vr0, $vr4, 24
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; CHECK-NEXT: vsrai.w $vr0, $vr0, 24
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; CHECK-NEXT: vst $vr0, $a1, 48
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; CHECK-NEXT: vst $vr3, $a1, 32
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; CHECK-NEXT: vst $vr2, $a1, 16
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; CHECK-NEXT: vst $vr1, $a1, 0
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; CHECK-NEXT: ret
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entry:
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%A = load <16 x i8>, ptr %ptr
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%B = sext <16 x i8> %A to <16 x i32>
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store <16 x i32> %B, ptr %dst
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ret void
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}
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define void @load_sext_16i8_to_16i64(ptr %ptr, ptr %dst) {
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; CHECK-LABEL: load_sext_16i8_to_16i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a0, 0
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0
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; CHECK-NEXT: vinsgr2vr.d $vr1, $a0, 0
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
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; CHECK-NEXT: vinsgr2vr.d $vr1, $a0, 1
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; CHECK-NEXT: vslli.d $vr1, $vr1, 56
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; CHECK-NEXT: vsrai.d $vr1, $vr1, 56
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 2
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; CHECK-NEXT: vinsgr2vr.d $vr2, $a0, 0
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 3
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; CHECK-NEXT: vinsgr2vr.d $vr2, $a0, 1
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; CHECK-NEXT: vslli.d $vr2, $vr2, 56
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; CHECK-NEXT: vsrai.d $vr2, $vr2, 56
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 4
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; CHECK-NEXT: vinsgr2vr.d $vr3, $a0, 0
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 5
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; CHECK-NEXT: vinsgr2vr.d $vr3, $a0, 1
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; CHECK-NEXT: vslli.d $vr3, $vr3, 56
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; CHECK-NEXT: vsrai.d $vr3, $vr3, 56
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 6
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; CHECK-NEXT: vinsgr2vr.d $vr4, $a0, 0
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 7
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; CHECK-NEXT: vinsgr2vr.d $vr4, $a0, 1
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; CHECK-NEXT: vslli.d $vr4, $vr4, 56
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; CHECK-NEXT: vsrai.d $vr4, $vr4, 56
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 8
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; CHECK-NEXT: vinsgr2vr.d $vr5, $a0, 0
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 9
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; CHECK-NEXT: vinsgr2vr.d $vr5, $a0, 1
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; CHECK-NEXT: vslli.d $vr5, $vr5, 56
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; CHECK-NEXT: vsrai.d $vr5, $vr5, 56
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 10
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; CHECK-NEXT: vinsgr2vr.d $vr6, $a0, 0
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 11
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; CHECK-NEXT: vinsgr2vr.d $vr6, $a0, 1
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; CHECK-NEXT: vslli.d $vr6, $vr6, 56
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; CHECK-NEXT: vsrai.d $vr6, $vr6, 56
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 12
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; CHECK-NEXT: vinsgr2vr.d $vr7, $a0, 0
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 13
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; CHECK-NEXT: vinsgr2vr.d $vr7, $a0, 1
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; CHECK-NEXT: vslli.d $vr7, $vr7, 56
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; CHECK-NEXT: vsrai.d $vr7, $vr7, 56
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 14
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; CHECK-NEXT: vinsgr2vr.d $vr8, $a0, 0
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; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 15
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; CHECK-NEXT: vinsgr2vr.d $vr8, $a0, 1
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; CHECK-NEXT: vslli.d $vr0, $vr8, 56
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; CHECK-NEXT: vsrai.d $vr0, $vr0, 56
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; CHECK-NEXT: vst $vr0, $a1, 112
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; CHECK-NEXT: vst $vr7, $a1, 96
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; CHECK-NEXT: vst $vr6, $a1, 80
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; CHECK-NEXT: vst $vr5, $a1, 64
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; CHECK-NEXT: vst $vr4, $a1, 48
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; CHECK-NEXT: vst $vr3, $a1, 32
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; CHECK-NEXT: vst $vr2, $a1, 16
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; CHECK-NEXT: vst $vr1, $a1, 0
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; CHECK-NEXT: ret
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entry:
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%A = load <16 x i8>, ptr %ptr
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%B = sext <16 x i8> %A to <16 x i64>
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store <16 x i64> %B, ptr %dst
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ret void
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}
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define void @load_sext_8i16_to_8i32(ptr %ptr, ptr %dst) {
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; CHECK-LABEL: load_sext_8i16_to_8i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a0, 0
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; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 0
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; CHECK-NEXT: vinsgr2vr.w $vr1, $a0, 0
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; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 1
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; CHECK-NEXT: vinsgr2vr.w $vr1, $a0, 1
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; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 2
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; CHECK-NEXT: vinsgr2vr.w $vr1, $a0, 2
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; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 3
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; CHECK-NEXT: vinsgr2vr.w $vr1, $a0, 3
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; CHECK-NEXT: vslli.w $vr1, $vr1, 16
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; CHECK-NEXT: vsrai.w $vr1, $vr1, 16
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; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 4
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; CHECK-NEXT: vinsgr2vr.w $vr2, $a0, 0
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; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 5
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; CHECK-NEXT: vinsgr2vr.w $vr2, $a0, 1
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; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 6
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; CHECK-NEXT: vinsgr2vr.w $vr2, $a0, 2
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; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 7
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; CHECK-NEXT: vinsgr2vr.w $vr2, $a0, 3
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; CHECK-NEXT: vslli.w $vr0, $vr2, 16
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; CHECK-NEXT: vsrai.w $vr0, $vr0, 16
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; CHECK-NEXT: vst $vr0, $a1, 16
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; CHECK-NEXT: vst $vr1, $a1, 0
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; CHECK-NEXT: ret
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entry:
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%A = load <8 x i16>, ptr %ptr
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%B = sext <8 x i16> %A to <8 x i32>
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store <8 x i32> %B, ptr %dst
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ret void
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}
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define void @load_sext_8i16_to_8i64(ptr %ptr, ptr %dst) {
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; CHECK-LABEL: load_sext_8i16_to_8i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a0, 0
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; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 0
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; CHECK-NEXT: vinsgr2vr.d $vr1, $a0, 0
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; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 1
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; CHECK-NEXT: vinsgr2vr.d $vr1, $a0, 1
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; CHECK-NEXT: vslli.d $vr1, $vr1, 48
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; CHECK-NEXT: vsrai.d $vr1, $vr1, 48
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; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 2
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; CHECK-NEXT: vinsgr2vr.d $vr2, $a0, 0
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; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 3
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; CHECK-NEXT: vinsgr2vr.d $vr2, $a0, 1
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; CHECK-NEXT: vslli.d $vr2, $vr2, 48
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; CHECK-NEXT: vsrai.d $vr2, $vr2, 48
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; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 4
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; CHECK-NEXT: vinsgr2vr.d $vr3, $a0, 0
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; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 5
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; CHECK-NEXT: vinsgr2vr.d $vr3, $a0, 1
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; CHECK-NEXT: vslli.d $vr3, $vr3, 48
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; CHECK-NEXT: vsrai.d $vr3, $vr3, 48
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; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 6
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; CHECK-NEXT: vinsgr2vr.d $vr4, $a0, 0
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; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 7
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; CHECK-NEXT: vinsgr2vr.d $vr4, $a0, 1
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; CHECK-NEXT: vslli.d $vr0, $vr4, 48
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; CHECK-NEXT: vsrai.d $vr0, $vr0, 48
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; CHECK-NEXT: vst $vr0, $a1, 48
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; CHECK-NEXT: vst $vr3, $a1, 32
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; CHECK-NEXT: vst $vr2, $a1, 16
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; CHECK-NEXT: vst $vr1, $a1, 0
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; CHECK-NEXT: ret
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entry:
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%A = load <8 x i16>, ptr %ptr
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%B = sext <8 x i16> %A to <8 x i64>
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store <8 x i64> %B, ptr %dst
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ret void
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}
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define void @load_sext_4i32_to_4i64(ptr %ptr, ptr %dst) {
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; CHECK-LABEL: load_sext_4i32_to_4i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a0, 0
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; CHECK-NEXT: vpickve2gr.w $a0, $vr0, 0
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; CHECK-NEXT: vinsgr2vr.d $vr1, $a0, 0
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; CHECK-NEXT: vpickve2gr.w $a0, $vr0, 1
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; CHECK-NEXT: vinsgr2vr.d $vr1, $a0, 1
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; CHECK-NEXT: vslli.d $vr1, $vr1, 32
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; CHECK-NEXT: vsrai.d $vr1, $vr1, 32
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; CHECK-NEXT: vpickve2gr.w $a0, $vr0, 2
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; CHECK-NEXT: vinsgr2vr.d $vr2, $a0, 0
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; CHECK-NEXT: vpickve2gr.w $a0, $vr0, 3
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; CHECK-NEXT: vinsgr2vr.d $vr2, $a0, 1
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; CHECK-NEXT: vslli.d $vr0, $vr2, 32
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; CHECK-NEXT: vsrai.d $vr0, $vr0, 32
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; CHECK-NEXT: vst $vr0, $a1, 16
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; CHECK-NEXT: vst $vr1, $a1, 0
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; CHECK-NEXT: ret
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entry:
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%A = load <4 x i32>, ptr %ptr
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%B = sext <4 x i32> %A to <4 x i64>
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store <4 x i64> %B, ptr %dst
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ret void
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}
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