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davemgreendavemgreen
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[AArch64][GlobalISel] Remove min/max v2s64 clamp
We can now lower the icmp, allowing us to remove the FIXME.
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4 files changed

+89
-84
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4 files changed

+89
-84
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‎llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -251,9 +251,6 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
251251
.clampNumElements(0, v8s8, v16s8)
252252
.clampNumElements(0, v4s16, v8s16)
253253
.clampNumElements(0, v2s32, v4s32)
254-
// FIXME: This sholdn't be needed as v2s64 types are going to
255-
// be expanded anyway, but G_ICMP doesn't support splitting vectors yet
256-
.clampNumElements(0, v2s64, v2s64)
257254
.lower();
258255

259256
getActionDefinitionsBuilder(

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-min-max.mir

Lines changed: 40 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -248,17 +248,19 @@ body: |
248248
; CHECK-NEXT: {{ $}}
249249
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
250250
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(slt), [[DEF]](<2 x s64>), [[DEF]]
251+
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(slt), [[DEF]](<2 x s64>), [[DEF]]
252+
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP]], 1
253+
; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP1]], 1
251254
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
252255
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
253-
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
254-
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP]]
255-
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
256-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND1]]
257-
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(slt), [[DEF]](<2 x s64>), [[DEF]]
258-
; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR]]
259-
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP1]]
256+
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG]], [[BUILD_VECTOR]]
257+
; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG1]], [[BUILD_VECTOR]]
258+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[SEXT_INREG]]
259+
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[SEXT_INREG1]]
260+
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
260261
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]]
261-
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND2]], [[AND3]]
262+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND2]]
263+
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND1]], [[AND3]]
262264
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
263265
; CHECK-NEXT: G_STORE [[OR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>), align 32)
264266
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
@@ -518,17 +520,19 @@ body: |
518520
; CHECK-NEXT: {{ $}}
519521
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
520522
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ult), [[DEF]](<2 x s64>), [[DEF]]
523+
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ult), [[DEF]](<2 x s64>), [[DEF]]
524+
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP]], 1
525+
; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP1]], 1
521526
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
522527
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
523-
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
524-
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP]]
525-
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
526-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND1]]
527-
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ult), [[DEF]](<2 x s64>), [[DEF]]
528-
; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR]]
529-
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP1]]
528+
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG]], [[BUILD_VECTOR]]
529+
; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG1]], [[BUILD_VECTOR]]
530+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[SEXT_INREG]]
531+
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[SEXT_INREG1]]
532+
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
530533
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]]
531-
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND2]], [[AND3]]
534+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND2]]
535+
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND1]], [[AND3]]
532536
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
533537
; CHECK-NEXT: G_STORE [[OR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>), align 32)
534538
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
@@ -788,17 +792,19 @@ body: |
788792
; CHECK-NEXT: {{ $}}
789793
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
790794
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sgt), [[DEF]](<2 x s64>), [[DEF]]
795+
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sgt), [[DEF]](<2 x s64>), [[DEF]]
796+
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP]], 1
797+
; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP1]], 1
791798
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
792799
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
793-
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
794-
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP]]
795-
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
796-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND1]]
797-
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sgt), [[DEF]](<2 x s64>), [[DEF]]
798-
; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR]]
799-
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP1]]
800+
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG]], [[BUILD_VECTOR]]
801+
; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG1]], [[BUILD_VECTOR]]
802+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[SEXT_INREG]]
803+
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[SEXT_INREG1]]
804+
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
800805
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]]
801-
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND2]], [[AND3]]
806+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND2]]
807+
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND1]], [[AND3]]
802808
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
803809
; CHECK-NEXT: G_STORE [[OR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>), align 32)
804810
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
@@ -1058,17 +1064,19 @@ body: |
10581064
; CHECK-NEXT: {{ $}}
10591065
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
10601066
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ugt), [[DEF]](<2 x s64>), [[DEF]]
1067+
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ugt), [[DEF]](<2 x s64>), [[DEF]]
1068+
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP]], 1
1069+
; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP1]], 1
10611070
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
10621071
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
1063-
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
1064-
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP]]
1065-
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
1066-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND1]]
1067-
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ugt), [[DEF]](<2 x s64>), [[DEF]]
1068-
; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR]]
1069-
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP1]]
1072+
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG]], [[BUILD_VECTOR]]
1073+
; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG1]], [[BUILD_VECTOR]]
1074+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[SEXT_INREG]]
1075+
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[SEXT_INREG1]]
1076+
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
10701077
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]]
1071-
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND2]], [[AND3]]
1078+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND2]]
1079+
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND1]], [[AND3]]
10721080
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
10731081
; CHECK-NEXT: G_STORE [[OR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>), align 32)
10741082
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16

‎llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll

Lines changed: 45 additions & 45 deletions
Original file line numberDiff line numberDiff line change
@@ -388,29 +388,29 @@ define <5 x i32> @test_signed_v5f64_v5i32(<5 x double> %f) {
388388
; CHECK-GI-NEXT: fcvtzs v1.2d, v2.2d
389389
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI12_1]
390390
; CHECK-GI-NEXT: adrp x8, .LCPI12_0
391+
; CHECK-GI-NEXT: cmgt v6.2d, v2.2d, v3.2d
391392
; CHECK-GI-NEXT: cmgt v4.2d, v2.2d, v0.2d
392393
; CHECK-GI-NEXT: cmgt v5.2d, v2.2d, v1.2d
393394
; CHECK-GI-NEXT: bif v0.16b, v2.16b, v4.16b
394395
; CHECK-GI-NEXT: bif v1.16b, v2.16b, v5.16b
395-
; CHECK-GI-NEXT: cmgt v4.2d, v2.2d, v3.2d
396-
; CHECK-GI-NEXT: ldr q5, [x8, :lo12:.LCPI12_0]
397-
; CHECK-GI-NEXT: bit v2.16b, v3.16b, v4.16b
398-
; CHECK-GI-NEXT: cmgt v3.2d, v0.2d, v5.2d
399-
; CHECK-GI-NEXT: cmgt v4.2d, v1.2d, v5.2d
400-
; CHECK-GI-NEXT: bif v0.16b, v5.16b, v3.16b
401-
; CHECK-GI-NEXT: bif v1.16b, v5.16b, v4.16b
402-
; CHECK-GI-NEXT: cmgt v3.2d, v2.2d, v5.2d
403-
; CHECK-GI-NEXT: bif v2.16b, v5.16b, v3.16b
396+
; CHECK-GI-NEXT: ldr q4, [x8, :lo12:.LCPI12_0]
397+
; CHECK-GI-NEXT: bit v2.16b, v3.16b, v6.16b
398+
; CHECK-GI-NEXT: cmgt v3.2d, v0.2d, v4.2d
399+
; CHECK-GI-NEXT: cmgt v5.2d, v1.2d, v4.2d
400+
; CHECK-GI-NEXT: cmgt v6.2d, v2.2d, v4.2d
401+
; CHECK-GI-NEXT: bif v0.16b, v4.16b, v3.16b
402+
; CHECK-GI-NEXT: bif v1.16b, v4.16b, v5.16b
403+
; CHECK-GI-NEXT: bif v2.16b, v4.16b, v6.16b
404404
; CHECK-GI-NEXT: mov d3, v0.d[1]
405405
; CHECK-GI-NEXT: mov d4, v1.d[1]
406406
; CHECK-GI-NEXT: fmov x0, d0
407+
; CHECK-GI-NEXT: fmov x4, d2
407408
; CHECK-GI-NEXT: fmov x2, d1
408409
; CHECK-GI-NEXT: // kill: def $w0 killed $w0 killed $x0
409410
; CHECK-GI-NEXT: // kill: def $w2 killed $w2 killed $x2
410-
; CHECK-GI-NEXT: fmov x4, d2
411+
; CHECK-GI-NEXT: // kill: def $w4 killed $w4 killed $x4
411412
; CHECK-GI-NEXT: fmov x1, d3
412413
; CHECK-GI-NEXT: fmov x3, d4
413-
; CHECK-GI-NEXT: // kill: def $w4 killed $w4 killed $x4
414414
; CHECK-GI-NEXT: // kill: def $w1 killed $w1 killed $x1
415415
; CHECK-GI-NEXT: // kill: def $w3 killed $w3 killed $x3
416416
; CHECK-GI-NEXT: ret
@@ -5236,6 +5236,7 @@ define <16 x i8> @test_signed_v16f64_v16i8(<16 x double> %f) {
52365236
; CHECK-GI-NEXT: adrp x8, .LCPI83_0
52375237
; CHECK-GI-NEXT: fcvtzs v6.2d, v6.2d
52385238
; CHECK-GI-NEXT: fcvtzs v7.2d, v7.2d
5239+
; CHECK-GI-NEXT: ldr q25, [x8, :lo12:.LCPI83_0]
52395240
; CHECK-GI-NEXT: cmgt v17.2d, v16.2d, v0.2d
52405241
; CHECK-GI-NEXT: cmgt v18.2d, v16.2d, v1.2d
52415242
; CHECK-GI-NEXT: cmgt v19.2d, v16.2d, v2.2d
@@ -5246,29 +5247,28 @@ define <16 x i8> @test_signed_v16f64_v16i8(<16 x double> %f) {
52465247
; CHECK-GI-NEXT: cmgt v24.2d, v16.2d, v7.2d
52475248
; CHECK-GI-NEXT: bif v0.16b, v16.16b, v17.16b
52485249
; CHECK-GI-NEXT: bif v1.16b, v16.16b, v18.16b
5249-
; CHECK-GI-NEXT: ldr q17, [x8, :lo12:.LCPI83_0]
52505250
; CHECK-GI-NEXT: bif v2.16b, v16.16b, v19.16b
52515251
; CHECK-GI-NEXT: bif v3.16b, v16.16b, v20.16b
52525252
; CHECK-GI-NEXT: bif v4.16b, v16.16b, v21.16b
52535253
; CHECK-GI-NEXT: bif v5.16b, v16.16b, v22.16b
52545254
; CHECK-GI-NEXT: bif v6.16b, v16.16b, v23.16b
52555255
; CHECK-GI-NEXT: bif v7.16b, v16.16b, v24.16b
5256-
; CHECK-GI-NEXT: cmgt v16.2d, v0.2d, v17.2d
5257-
; CHECK-GI-NEXT: cmgt v18.2d, v1.2d, v17.2d
5258-
; CHECK-GI-NEXT: cmgt v19.2d, v2.2d, v17.2d
5259-
; CHECK-GI-NEXT: cmgt v20.2d, v3.2d, v17.2d
5260-
; CHECK-GI-NEXT: cmgt v21.2d, v4.2d, v17.2d
5261-
; CHECK-GI-NEXT: cmgt v22.2d, v5.2d, v17.2d
5262-
; CHECK-GI-NEXT: cmgt v23.2d, v6.2d, v17.2d
5263-
; CHECK-GI-NEXT: cmgt v24.2d, v7.2d, v17.2d
5264-
; CHECK-GI-NEXT: bif v0.16b, v17.16b, v16.16b
5265-
; CHECK-GI-NEXT: bif v1.16b, v17.16b, v18.16b
5266-
; CHECK-GI-NEXT: bif v2.16b, v17.16b, v19.16b
5267-
; CHECK-GI-NEXT: bif v3.16b, v17.16b, v20.16b
5268-
; CHECK-GI-NEXT: bif v4.16b, v17.16b, v21.16b
5269-
; CHECK-GI-NEXT: bif v5.16b, v17.16b, v22.16b
5270-
; CHECK-GI-NEXT: bif v6.16b, v17.16b, v23.16b
5271-
; CHECK-GI-NEXT: bif v7.16b, v17.16b, v24.16b
5256+
; CHECK-GI-NEXT: cmgt v16.2d, v0.2d, v25.2d
5257+
; CHECK-GI-NEXT: cmgt v17.2d, v1.2d, v25.2d
5258+
; CHECK-GI-NEXT: cmgt v18.2d, v2.2d, v25.2d
5259+
; CHECK-GI-NEXT: cmgt v19.2d, v3.2d, v25.2d
5260+
; CHECK-GI-NEXT: cmgt v20.2d, v4.2d, v25.2d
5261+
; CHECK-GI-NEXT: cmgt v21.2d, v5.2d, v25.2d
5262+
; CHECK-GI-NEXT: cmgt v22.2d, v6.2d, v25.2d
5263+
; CHECK-GI-NEXT: cmgt v23.2d, v7.2d, v25.2d
5264+
; CHECK-GI-NEXT: bif v0.16b, v25.16b, v16.16b
5265+
; CHECK-GI-NEXT: bif v1.16b, v25.16b, v17.16b
5266+
; CHECK-GI-NEXT: bif v2.16b, v25.16b, v18.16b
5267+
; CHECK-GI-NEXT: bif v3.16b, v25.16b, v19.16b
5268+
; CHECK-GI-NEXT: bif v4.16b, v25.16b, v20.16b
5269+
; CHECK-GI-NEXT: bif v5.16b, v25.16b, v21.16b
5270+
; CHECK-GI-NEXT: bif v6.16b, v25.16b, v22.16b
5271+
; CHECK-GI-NEXT: bif v7.16b, v25.16b, v23.16b
52725272
; CHECK-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s
52735273
; CHECK-GI-NEXT: uzp1 v1.4s, v2.4s, v3.4s
52745274
; CHECK-GI-NEXT: uzp1 v2.4s, v4.4s, v5.4s
@@ -5505,6 +5505,7 @@ define <16 x i16> @test_signed_v16f64_v16i16(<16 x double> %f) {
55055505
; CHECK-GI-NEXT: adrp x8, .LCPI85_0
55065506
; CHECK-GI-NEXT: fcvtzs v6.2d, v6.2d
55075507
; CHECK-GI-NEXT: fcvtzs v7.2d, v7.2d
5508+
; CHECK-GI-NEXT: ldr q25, [x8, :lo12:.LCPI85_0]
55085509
; CHECK-GI-NEXT: cmgt v17.2d, v16.2d, v0.2d
55095510
; CHECK-GI-NEXT: cmgt v18.2d, v16.2d, v1.2d
55105511
; CHECK-GI-NEXT: cmgt v19.2d, v16.2d, v2.2d
@@ -5515,29 +5516,28 @@ define <16 x i16> @test_signed_v16f64_v16i16(<16 x double> %f) {
55155516
; CHECK-GI-NEXT: cmgt v24.2d, v16.2d, v7.2d
55165517
; CHECK-GI-NEXT: bif v0.16b, v16.16b, v17.16b
55175518
; CHECK-GI-NEXT: bif v1.16b, v16.16b, v18.16b
5518-
; CHECK-GI-NEXT: ldr q17, [x8, :lo12:.LCPI85_0]
55195519
; CHECK-GI-NEXT: bif v2.16b, v16.16b, v19.16b
55205520
; CHECK-GI-NEXT: bif v3.16b, v16.16b, v20.16b
55215521
; CHECK-GI-NEXT: bif v4.16b, v16.16b, v21.16b
55225522
; CHECK-GI-NEXT: bif v5.16b, v16.16b, v22.16b
55235523
; CHECK-GI-NEXT: bif v6.16b, v16.16b, v23.16b
55245524
; CHECK-GI-NEXT: bif v7.16b, v16.16b, v24.16b
5525-
; CHECK-GI-NEXT: cmgt v16.2d, v0.2d, v17.2d
5526-
; CHECK-GI-NEXT: cmgt v18.2d, v1.2d, v17.2d
5527-
; CHECK-GI-NEXT: cmgt v19.2d, v2.2d, v17.2d
5528-
; CHECK-GI-NEXT: cmgt v20.2d, v3.2d, v17.2d
5529-
; CHECK-GI-NEXT: cmgt v21.2d, v4.2d, v17.2d
5530-
; CHECK-GI-NEXT: cmgt v22.2d, v5.2d, v17.2d
5531-
; CHECK-GI-NEXT: cmgt v23.2d, v6.2d, v17.2d
5532-
; CHECK-GI-NEXT: cmgt v24.2d, v7.2d, v17.2d
5533-
; CHECK-GI-NEXT: bif v0.16b, v17.16b, v16.16b
5534-
; CHECK-GI-NEXT: bif v1.16b, v17.16b, v18.16b
5535-
; CHECK-GI-NEXT: bif v2.16b, v17.16b, v19.16b
5536-
; CHECK-GI-NEXT: bif v3.16b, v17.16b, v20.16b
5537-
; CHECK-GI-NEXT: bif v4.16b, v17.16b, v21.16b
5538-
; CHECK-GI-NEXT: bif v5.16b, v17.16b, v22.16b
5539-
; CHECK-GI-NEXT: bif v6.16b, v17.16b, v23.16b
5540-
; CHECK-GI-NEXT: bif v7.16b, v17.16b, v24.16b
5525+
; CHECK-GI-NEXT: cmgt v16.2d, v0.2d, v25.2d
5526+
; CHECK-GI-NEXT: cmgt v17.2d, v1.2d, v25.2d
5527+
; CHECK-GI-NEXT: cmgt v18.2d, v2.2d, v25.2d
5528+
; CHECK-GI-NEXT: cmgt v19.2d, v3.2d, v25.2d
5529+
; CHECK-GI-NEXT: cmgt v20.2d, v4.2d, v25.2d
5530+
; CHECK-GI-NEXT: cmgt v21.2d, v5.2d, v25.2d
5531+
; CHECK-GI-NEXT: cmgt v22.2d, v6.2d, v25.2d
5532+
; CHECK-GI-NEXT: cmgt v23.2d, v7.2d, v25.2d
5533+
; CHECK-GI-NEXT: bif v0.16b, v25.16b, v16.16b
5534+
; CHECK-GI-NEXT: bif v1.16b, v25.16b, v17.16b
5535+
; CHECK-GI-NEXT: bif v2.16b, v25.16b, v18.16b
5536+
; CHECK-GI-NEXT: bif v3.16b, v25.16b, v19.16b
5537+
; CHECK-GI-NEXT: bif v4.16b, v25.16b, v20.16b
5538+
; CHECK-GI-NEXT: bif v5.16b, v25.16b, v21.16b
5539+
; CHECK-GI-NEXT: bif v6.16b, v25.16b, v22.16b
5540+
; CHECK-GI-NEXT: bif v7.16b, v25.16b, v23.16b
55415541
; CHECK-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s
55425542
; CHECK-GI-NEXT: uzp1 v1.4s, v2.4s, v3.4s
55435543
; CHECK-GI-NEXT: uzp1 v2.4s, v4.4s, v5.4s

‎llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -367,22 +367,22 @@ define <5 x i32> @test_unsigned_v5f64_v5i32(<5 x double> %f) {
367367
; CHECK-GI-NEXT: fcvtzu v3.2d, v4.2d
368368
; CHECK-GI-NEXT: fcvtzu v0.2d, v0.2d
369369
; CHECK-GI-NEXT: fcvtzu v2.2d, v2.2d
370+
; CHECK-GI-NEXT: cmhi v6.2d, v1.2d, v3.2d
370371
; CHECK-GI-NEXT: cmhi v4.2d, v1.2d, v0.2d
371372
; CHECK-GI-NEXT: cmhi v5.2d, v1.2d, v2.2d
372373
; CHECK-GI-NEXT: bif v0.16b, v1.16b, v4.16b
373374
; CHECK-GI-NEXT: bif v2.16b, v1.16b, v5.16b
374-
; CHECK-GI-NEXT: cmhi v4.2d, v1.2d, v3.2d
375-
; CHECK-GI-NEXT: bit v1.16b, v3.16b, v4.16b
375+
; CHECK-GI-NEXT: bit v1.16b, v3.16b, v6.16b
376376
; CHECK-GI-NEXT: mov d3, v0.d[1]
377377
; CHECK-GI-NEXT: mov d4, v2.d[1]
378+
; CHECK-GI-NEXT: fmov x4, d1
378379
; CHECK-GI-NEXT: fmov x0, d0
379380
; CHECK-GI-NEXT: fmov x2, d2
381+
; CHECK-GI-NEXT: // kill: def $w4 killed $w4 killed $x4
380382
; CHECK-GI-NEXT: // kill: def $w0 killed $w0 killed $x0
381383
; CHECK-GI-NEXT: // kill: def $w2 killed $w2 killed $x2
382-
; CHECK-GI-NEXT: fmov x4, d1
383384
; CHECK-GI-NEXT: fmov x1, d3
384385
; CHECK-GI-NEXT: fmov x3, d4
385-
; CHECK-GI-NEXT: // kill: def $w4 killed $w4 killed $x4
386386
; CHECK-GI-NEXT: // kill: def $w1 killed $w1 killed $x1
387387
; CHECK-GI-NEXT: // kill: def $w3 killed $w3 killed $x3
388388
; CHECK-GI-NEXT: ret

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