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[AMDGPU] Add VDSDIR instructions for GFX12 (#75197)
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12 files changed

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-150
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12 files changed

+679
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‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

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@@ -166,6 +166,8 @@ class AMDGPUOperand : public MCParsedAsmOperand {
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ImmTyEndpgm,
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ImmTyWaitVDST,
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ImmTyWaitEXP,
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ImmTyWaitVAVDst,
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ImmTyWaitVMVSrc,
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};
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// Immediate operand kind.
@@ -909,6 +911,8 @@ class AMDGPUOperand : public MCParsedAsmOperand {
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bool isEndpgm() const;
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bool isWaitVDST() const;
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bool isWaitEXP() const;
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bool isWaitVAVDst() const;
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bool isWaitVMVSrc() const;
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auto getPredicate(std::function<bool(const AMDGPUOperand &Op)> P) const {
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return std::bind(P, *this);
@@ -1029,6 +1033,7 @@ class AMDGPUOperand : public MCParsedAsmOperand {
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}
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static void printImmTy(raw_ostream& OS, ImmTy Type) {
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// clang-format off
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switch (Type) {
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case ImmTyNone: OS << "None"; break;
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case ImmTyGDS: OS << "GDS"; break;
@@ -1086,7 +1091,10 @@ class AMDGPUOperand : public MCParsedAsmOperand {
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case ImmTyEndpgm: OS << "Endpgm"; break;
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case ImmTyWaitVDST: OS << "WaitVDST"; break;
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case ImmTyWaitEXP: OS << "WaitEXP"; break;
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case ImmTyWaitVAVDst: OS << "WaitVAVDst"; break;
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case ImmTyWaitVMVSrc: OS << "WaitVMVSrc"; break;
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}
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// clang-format on
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}
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void print(raw_ostream &OS) const override {
@@ -9192,6 +9200,14 @@ bool AMDGPUOperand::isWaitVDST() const {
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return isImmTy(ImmTyWaitVDST) && isUInt<4>(getImm());
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}
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bool AMDGPUOperand::isWaitVAVDst() const {
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return isImmTy(ImmTyWaitVAVDst) && isUInt<4>(getImm());
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}
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bool AMDGPUOperand::isWaitVMVSrc() const {
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return isImmTy(ImmTyWaitVMVSrc) && isUInt<1>(getImm());
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}
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//===----------------------------------------------------------------------===//
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// VINTERP
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//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AMDGPU/DSDIRInstructions.td

Lines changed: 191 additions & 0 deletions
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@@ -0,0 +1,191 @@
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//===-- DSDIRInstructions.td - LDS/VDS Direct Instruction Definitions -----===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// LDSDIR/VDSDIR encoding (LDSDIR is gfx11, VDSDIR is gfx12+)
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//===----------------------------------------------------------------------===//
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class LDSDIRe<bits<2> op, bit is_direct> : Enc32 {
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// encoding fields
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bits<2> attrchan;
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bits<6> attr;
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bits<4> waitvdst;
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bits<8> vdst;
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// encoding
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let Inst{31-24} = 0xce; // encoding
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let Inst{23-22} = 0x0; // reserved
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let Inst{21-20} = op;
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let Inst{19-16} = waitvdst;
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let Inst{15-10} = !if(is_direct, ?, attr);
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let Inst{9-8} = !if(is_direct, ?, attrchan);
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let Inst{7-0} = vdst;
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}
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class VDSDIRe<bits<2> op, bit is_direct> : Enc32 {
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// encoding fields
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bits<2> attrchan;
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bits<6> attr;
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bits<4> waitvdst;
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bits<8> vdst;
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bits<1> waitvsrc;
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// encoding
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let Inst{31-24} = 0xce; // encoding
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let Inst{23} = waitvsrc;
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let Inst{22} = 0x0; // reserved
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let Inst{21-20} = op;
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let Inst{19-16} = waitvdst;
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let Inst{15-10} = !if(is_direct, ?, attr);
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let Inst{9-8} = !if(is_direct, ?, attrchan);
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let Inst{7-0} = vdst;
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}
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//===----------------------------------------------------------------------===//
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// LDSDIR/VDSDIR Classes
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//===----------------------------------------------------------------------===//
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class LDSDIR_getIns<bit direct> {
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dag ret = !if(direct,
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(ins wait_vdst:$waitvdst),
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(ins InterpAttr:$attr, InterpAttrChan:$attrchan, wait_vdst:$waitvdst)
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);
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}
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class VDSDIR_getIns<bit direct> {
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dag ret = !if(direct,
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(ins wait_va_vdst:$waitvdst, wait_va_vsrc:$waitvsrc),
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(ins InterpAttr:$attr, InterpAttrChan:$attrchan, wait_va_vdst:$waitvdst,
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wait_va_vsrc:$waitvsrc)
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);
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}
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class DSDIR_Common<string opName, string asm = "", dag ins, bit direct> :
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InstSI<(outs VGPR_32:$vdst), ins, asm> {
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let LDSDIR = 1;
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let EXP_CNT = 1;
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let hasSideEffects = 0;
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let mayLoad = 1;
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let mayStore = 0;
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string Mnemonic = opName;
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let UseNamedOperandTable = 1;
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let Uses = [M0, EXEC];
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let DisableWQM = 0;
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let SchedRW = [WriteLDS];
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bit is_direct;
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let is_direct = direct;
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}
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class DSDIR_Pseudo<string opName, dag ins, bit direct> :
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DSDIR_Common<opName, "", ins, direct>,
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SIMCInstr<opName, SIEncodingFamily.NONE> {
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let isPseudo = 1;
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let isCodeGenOnly = 1;
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}
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class LDSDIR_getAsm<bit direct> {
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string ret = !if(direct,
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" $vdst$waitvdst",
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" $vdst, $attr$attrchan$waitvdst"
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);
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}
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class VDSDIR_getAsm<bit direct> {
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string ret = !if(direct,
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" $vdst$waitvdst$waitvsrc",
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" $vdst, $attr$attrchan$waitvdst$waitvsrc"
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);
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}
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class DSDIR_Real<DSDIR_Pseudo lds, dag ins, string asm, int subtarget> :
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DSDIR_Common<lds.Mnemonic,
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lds.Mnemonic # asm,
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ins,
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lds.is_direct>,
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SIMCInstr <lds.Mnemonic, subtarget> {
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let isPseudo = 0;
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let isCodeGenOnly = 0;
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}
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//===----------------------------------------------------------------------===//
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// LDS/VDS Direct Instructions
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//===----------------------------------------------------------------------===//
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let SubtargetPredicate = isGFX11Only in {
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def LDS_DIRECT_LOAD : DSDIR_Pseudo<"lds_direct_load", LDSDIR_getIns<1>.ret, 1>;
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def LDS_PARAM_LOAD : DSDIR_Pseudo<"lds_param_load", LDSDIR_getIns<0>.ret, 0>;
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def : GCNPat <
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(f32 (int_amdgcn_lds_direct_load M0)),
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(LDS_DIRECT_LOAD 0)
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>;
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def : GCNPat <
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(f32 (int_amdgcn_lds_param_load timm:$attrchan, timm:$attr, M0)),
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(LDS_PARAM_LOAD timm:$attr, timm:$attrchan, 0)
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>;
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} // End SubtargetPredicate = isGFX11Only
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let SubtargetPredicate = isGFX12Plus in {
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def DS_DIRECT_LOAD : DSDIR_Pseudo<"ds_direct_load", VDSDIR_getIns<1>.ret, 1>;
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def DS_PARAM_LOAD : DSDIR_Pseudo<"ds_param_load", VDSDIR_getIns<0>.ret, 0>;
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def : GCNPat <
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(f32 (int_amdgcn_lds_direct_load M0)),
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(DS_DIRECT_LOAD 0, 1)
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>;
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def : GCNPat <
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(f32 (int_amdgcn_lds_param_load timm:$attrchan, timm:$attr, M0)),
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(DS_PARAM_LOAD timm:$attr, timm:$attrchan, 0, 1)
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>;
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} // End SubtargetPredicate = isGFX12Only
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//===----------------------------------------------------------------------===//
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// GFX11
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//===----------------------------------------------------------------------===//
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multiclass DSDIR_Real_gfx11<bits<2> op,
162+
DSDIR_Pseudo lds = !cast<DSDIR_Pseudo>(NAME)> {
163+
def _gfx11 : DSDIR_Real<lds, lds.InOperandList,
164+
LDSDIR_getAsm<lds.is_direct>.ret,
165+
SIEncodingFamily.GFX11>,
166+
LDSDIRe<op, lds.is_direct> {
167+
let AssemblerPredicate = isGFX11Only;
168+
let DecoderNamespace = "GFX11";
169+
}
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}
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defm LDS_PARAM_LOAD : DSDIR_Real_gfx11<0x0>;
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defm LDS_DIRECT_LOAD : DSDIR_Real_gfx11<0x1>;
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//===----------------------------------------------------------------------===//
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// GFX12+
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//===----------------------------------------------------------------------===//
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multiclass DSDIR_Real_gfx12<bits<2> op,
180+
DSDIR_Pseudo lds = !cast<DSDIR_Pseudo>(NAME)> {
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def _gfx12 : DSDIR_Real<lds, lds.InOperandList,
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VDSDIR_getAsm<lds.is_direct>.ret,
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SIEncodingFamily.GFX12>,
184+
VDSDIRe<op, lds.is_direct> {
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let AssemblerPredicate = isGFX12Plus;
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let DecoderNamespace = "GFX12";
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}
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}
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defm DS_PARAM_LOAD : DSDIR_Real_gfx12<0x0>;
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defm DS_DIRECT_LOAD : DSDIR_Real_gfx12<0x1>;

‎llvm/lib/Target/AMDGPU/LDSDIRInstructions.td

Lines changed: 0 additions & 116 deletions
This file was deleted.

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -639,6 +639,20 @@ void AMDGPUInstPrinter::printWaitVDST(const MCInst *MI, unsigned OpNo,
639639
printU4ImmDecOperand(MI, OpNo, O);
640640
}
641641

642+
void AMDGPUInstPrinter::printWaitVAVDst(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
644+
raw_ostream &O) {
645+
O << " wait_va_vdst:";
646+
printU4ImmDecOperand(MI, OpNo, O);
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}
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void AMDGPUInstPrinter::printWaitVMVSrc(const MCInst *MI, unsigned OpNo,
650+
const MCSubtargetInfo &STI,
651+
raw_ostream &O) {
652+
O << " wait_vm_vsrc:";
653+
printU4ImmDecOperand(MI, OpNo, O);
654+
}
655+
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void AMDGPUInstPrinter::printWaitEXP(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h

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@@ -161,6 +161,10 @@ class AMDGPUInstPrinter : public MCInstPrinter {
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raw_ostream &O);
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void printWaitEXP(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
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raw_ostream &O);
164+
void printWaitVAVDst(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printWaitVMVSrc(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI, raw_ostream &O);
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165169
void printExpSrcN(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
166170
raw_ostream &O, unsigned N);

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