self review:

    - the execution scope must be the second operand and not the final
      operand of the SPIRV instruction. this was missed as I did not
      realize that SPIRV-TOOLS was not enabled on my local machine but
      luckily got caught by the spir-v github tests

    - missing testcase for int64 in directx lowering and caught that
      Int64Ty was missing from the overload types of dxilop

Author: inbelic

llvm/lib/Target/DirectX/DXIL.td

@@ -807,8 +807,8 @@ def WaveReadLaneAt:  DXILOp<117, waveReadLaneAt> {
   let LLVMIntrinsic = int_dx_wave_readlane;
   let arguments = [OverloadTy, Int32Ty];
   let result = OverloadTy;
-  let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy, DoubleTy, Int1Ty, Int16Ty, Int32Ty]>];
-    let stages = [Stages<DXIL1_0, [all_stages]>];
+  let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy, DoubleTy, Int1Ty, Int16Ty, Int32Ty, Int64Ty]>];
+  let stages = [Stages<DXIL1_0, [all_stages]>];
   let attributes = [Attributes<DXIL1_0, [ReadNone]>];
 }
 

llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp

@@ -1777,9 +1777,9 @@ bool SPIRVInstructionSelector::selectWaveReadLaneAt(Register ResVReg,
                  TII.get(SPIRV::OpGroupNonUniformShuffle))
       .addDef(ResVReg)
       .addUse(GR.getSPIRVTypeID(ResType))
+      .addUse(GR.getOrCreateConstInt(3, I, IntTy, TII))
       .addUse(I.getOperand(2).getReg())
-      .addUse(I.getOperand(3).getReg())
-      .addUse(GR.getOrCreateConstInt(3, I, IntTy, TII));
+      .addUse(I.getOperand(3).getReg());
 }
 
 bool SPIRVInstructionSelector::selectBitreverse(Register ResVReg,

llvm/test/CodeGen/DirectX/WaveReadLaneAt.ll

@@ -44,10 +44,18 @@ entry:
   ret i32 %ret
 }
 
+define noundef i64 @wave_rla_i64(i64 noundef %expr, i32 noundef %idx) {
+entry:
+; CHECK: call i64 @dx.op.waveReadLaneAt.i64(i32 117, i64 %expr, i32 %idx)
+  %ret = call i64 @llvm.dx.wave.readlane.i64(i64 %expr, i32 %idx)
+  ret i64 %ret
+}
+
 declare half @llvm.dx.wave.readlane.f16(half, i32)
 declare float @llvm.dx.wave.readlane.f32(float, i32)
 declare double @llvm.dx.wave.readlane.f64(double, i32)
 
 declare i1 @llvm.dx.wave.readlane.i1(i1, i32)
 declare i16 @llvm.dx.wave.readlane.i16(i16, i32)
 declare i32 @llvm.dx.wave.readlane.i32(i32, i32)
+declare i64 @llvm.dx.wave.readlane.i64(i64, i32)

llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveReadLaneAt.ll

@@ -1,5 +1,5 @@
 ; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32v1.3-vulkan-unknown %s -o - | FileCheck %s
-; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-vulkan-unknown %s -o - -filetype=obj | spirv-val %}
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32v1.3-vulkan-unknown %s -o - -filetype=obj | spirv-val %}
 
 ; Test lowering to spir-v backend for various types and scalar/vector
 
@@ -9,29 +9,32 @@
 ; CHECK-DAG:   %[[#v4_bool:]] = OpTypeVector %[[#bool]] 4
 ; CHECK-DAG:   %[[#scope:]] = OpConstant %[[#uint]] 3
 
+; CHECK-LABEL: Begin function test_float
 ; CHECK:   %[[#fexpr:]] = OpFunctionParameter %[[#f32]]
 ; CHECK:   %[[#idx1:]] = OpFunctionParameter %[[#uint]]
-define float @test_1(float %fexpr, i32 %idx) {
+define float @test_float(float %fexpr, i32 %idx) {
 entry:
-; CHECK:   %[[#fret:]] = OpGroupNonUniformShuffle %[[#f32]] %[[#fexpr]] %[[#idx1]] %[[#scope]]
+; CHECK:   %[[#fret:]] = OpGroupNonUniformShuffle %[[#f32]] %[[#scope]] %[[#fexpr]] %[[#idx1]]
   %0 = call float @llvm.spv.wave.readlane.f32(float %fexpr, i32 %idx)
   ret float %0
 }
 
+; CHECK-LABEL: Begin function test_int
 ; CHECK:   %[[#iexpr:]] = OpFunctionParameter %[[#uint]]
 ; CHECK:   %[[#idx2:]] = OpFunctionParameter %[[#uint]]
-define i32 @test_2(i32 %iexpr, i32 %idx) {
+define i32 @test_int(i32 %iexpr, i32 %idx) {
 entry:
-; CHECK:   %[[#iret:]] = OpGroupNonUniformShuffle %[[#uint]] %[[#iexpr]] %[[#idx2]] %[[#scope]]
+; CHECK:   %[[#iret:]] = OpGroupNonUniformShuffle %[[#uint]] %[[#scope]] %[[#iexpr]] %[[#idx2]]
   %0 = call i32 @llvm.spv.wave.readlane.i32(i32 %iexpr, i32 %idx)
   ret i32 %0
 }
 
+; CHECK-LABEL: Begin function test_vbool
 ; CHECK:   %[[#vbexpr:]] = OpFunctionParameter %[[#v4_bool]]
 ; CHECK:   %[[#idx3:]] = OpFunctionParameter %[[#uint]]
-define <4 x i1> @test_3(<4 x i1> %vbexpr, i32 %idx) {
+define <4 x i1> @test_vbool(<4 x i1> %vbexpr, i32 %idx) {
 entry:
-; CHECK:   %[[#vbret:]] = OpGroupNonUniformShuffle %[[#v4_bool]] %[[#vbexpr]] %[[#idx3]] %[[#scope]]
+; CHECK:   %[[#vbret:]] = OpGroupNonUniformShuffle %[[#v4_bool]] %[[#scope]] %[[#vbexpr]] %[[#idx3]]
   %0 = call <4 x i1> @llvm.spv.wave.readlane.v4i1(<4 x i1> %vbexpr, i32 %idx)
   ret <4 x i1> %0
 }