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jwanggit86jwanggit86
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Ensure consistency between rsrc reg size and the r128 flag.
1 parent 5c3b75e commit 73836d7

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9 files changed

+183
-55
lines changed

9 files changed

+183
-55
lines changed

‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Lines changed: 62 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1781,6 +1781,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
17811781
bool validateMIMGD16(const MCInst &Inst);
17821782
bool validateMIMGDim(const MCInst &Inst, const OperandVector &Operands);
17831783
bool validateMIMGMSAA(const MCInst &Inst);
1784+
bool validateMIMGR128(const MCInst &Inst, const OperandVector &Operands);
17841785
bool validateOpSel(const MCInst &Inst);
17851786
bool validateTrue16OpSel(const MCInst &Inst);
17861787
bool validateNeg(const MCInst &Inst, AMDGPU::OpName OpName);
@@ -3974,6 +3975,64 @@ bool AMDGPUAsmParser::validateMIMGAddrSize(const MCInst &Inst,
39743975
return false;
39753976
}
39763977

3978+
bool AMDGPUAsmParser::validateMIMGR128(const MCInst &Inst,
3979+
const OperandVector &Operands) {
3980+
const unsigned Opc = Inst.getOpcode();
3981+
const MCInstrDesc &Desc = MII.get(Opc);
3982+
3983+
if ((Desc.TSFlags & MIMGFlags) == 0)
3984+
return true;
3985+
3986+
// image_bvh_intersect_ray instructions only support 128b RSRC reg
3987+
if (AMDGPU::getMIMGBaseOpcode(Opc)->BVH)
3988+
return true;
3989+
3990+
AMDGPU::OpName RSrcOpName = (Desc.TSFlags & SIInstrFlags::MIMG)
3991+
? AMDGPU::OpName::srsrc
3992+
: AMDGPU::OpName::rsrc;
3993+
int SrsrcIdx = AMDGPU::getNamedOperandIdx(Opc, RSrcOpName);
3994+
assert(SrsrcIdx != -1);
3995+
3996+
auto RsrcReg = Inst.getOperand(SrsrcIdx).getReg();
3997+
3998+
unsigned SrsrcRegSize = 4;
3999+
if (getMRI()->getRegClass(AMDGPU::SReg_256_XNULLRegClassID).contains(RsrcReg))
4000+
SrsrcRegSize = 8;
4001+
else {
4002+
switch (RsrcReg.id()) {
4003+
case TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_vi:
4004+
case TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_vi:
4005+
case TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15_vi:
4006+
case TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_gfx9plus:
4007+
case TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_gfx9plus:
4008+
case TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15_gfx9plus:
4009+
SrsrcRegSize = 8;
4010+
break;
4011+
default:
4012+
break;
4013+
}
4014+
}
4015+
4016+
int R128Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::r128);
4017+
bool IsR128 =
4018+
(hasMIMG_R128() && R128Idx != -1 && Inst.getOperand(R128Idx).getImm());
4019+
4020+
if (SrsrcRegSize == 8 && IsR128) {
4021+
auto Loc = getImmLoc(AMDGPUOperand::ImmTyR128A16, Operands);
4022+
Error(Loc, "r128 not allowed with 256-bit RSRC reg");
4023+
return false;
4024+
} else if (SrsrcRegSize == 4 && !IsR128) {
4025+
auto Loc = getInstLoc(Operands);
4026+
if (hasMIMG_R128())
4027+
Error(Loc,
4028+
"the RSRC reg should be 256-bit, or the r128 flag is required");
4029+
else
4030+
Error(Loc, "operands are not valid for this GPU or mode");
4031+
return false;
4032+
}
4033+
return true;
4034+
}
4035+
39774036
bool AMDGPUAsmParser::validateMIMGAtomicDMask(const MCInst &Inst) {
39784037

39794038
const unsigned Opc = Inst.getOpcode();
@@ -5191,6 +5250,9 @@ bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst,
51915250
"invalid dim; must be MSAA type");
51925251
return false;
51935252
}
5253+
if (!validateMIMGR128(Inst, Operands))
5254+
return false;
5255+
51945256
if (!validateMIMGDataSize(Inst, IDLoc)) {
51955257
return false;
51965258
}
@@ -9786,13 +9848,6 @@ unsigned AMDGPUAsmParser::validateTargetOperandClass(MCParsedAsmOperand &Op,
97869848
case MCK_SReg_256:
97879849
case MCK_SReg_512:
97889850
return Operand.isNull() ? Match_Success : Match_InvalidOperand;
9789-
case MCK_SReg_RSRC: {
9790-
if (Operand.isReg())
9791-
if (Operand.isRegClass(SReg_128_XNULLRegClassID) ||
9792-
Operand.isRegClass(SReg_256_XNULLRegClassID))
9793-
return Match_Success;
9794-
return Match_InvalidOperand;
9795-
}
97969851
default:
97979852
return Match_InvalidOperand;
97989853
}

‎llvm/test/MC/AMDGPU/gfx10_asm_mimg.s

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -42,9 +42,8 @@ image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D slc
4242
image_load v0, v255, s[0:7] dmask:0x6 dim:SQ_RSRC_IMG_1D d16
4343
; GFX10: image_load v0, v255, s[0:7] dmask:0x6 dim:SQ_RSRC_IMG_1D d16 ; encoding: [0x00,0x06,0x00,0xf0,0xff,0x00,0x00,0x80]
4444

45-
// FIXME: This test is incorrect because r128 assumes a 128-bit SRSRC.
46-
image_load v0, v255, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D r128
47-
; GFX10: image_load v0, v255, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D r128 ; encoding: [0x00,0x81,0x00,0xf0,0xff,0x00,0x00,0x00]
45+
image_load v0, v255, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
46+
; GFX10: image_load v0, v255, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x01,0x00,0xf0,0xff,0x00,0x00,0x00]
4847

4948
image_load v0, v[2:3], s[0:7] dmask:0x1 dim:2D
5049
; GFX10: image_load v0, v[2:3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x01,0x00,0xf0,0x02,0x00,0x00,0x00]

‎llvm/test/MC/AMDGPU/gfx10_asm_mimg_err.s

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -486,3 +486,33 @@ image_sample_o v[5:6], v[1:2], null, s[12:15] dmask:0x3 dim:SQ_RSRC_IMG_1D
486486

487487
image_sample_o v[5:6], v[1:2], s[8:15], null dmask:0x3 dim:SQ_RSRC_IMG_1D
488488
// NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
489+
490+
image_atomic_add v5, v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D r128
491+
// NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: r128 not allowed with 256-bit RSRC reg
492+
493+
image_atomic_add v5, v1, s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D
494+
// NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: the RSRC reg should be 256-bit, or the r128 flag is required
495+
496+
image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D r128
497+
// NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: r128 not allowed with 256-bit RSRC reg
498+
499+
image_load v[0:3], v0, s[0:3] dmask:0xf dim:SQ_RSRC_IMG_1D
500+
// NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: the RSRC reg should be 256-bit, or the r128 flag is required
501+
502+
image_store v[0:3], v[254:255], s[12:19] dmask:0xf dim:SQ_RSRC_IMG_2D r128
503+
// NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: r128 not allowed with 256-bit RSRC reg
504+
505+
image_store v[0:3], v[254:255], s[12:15] dmask:0xf dim:SQ_RSRC_IMG_2D
506+
// NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: the RSRC reg should be 256-bit, or the r128 flag is required
507+
508+
image_sample v[5:6], v1, s[8:15], s[12:15] dmask:0x3 dim:SQ_RSRC_IMG_1D r128
509+
// NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: r128 not allowed with 256-bit RSRC reg
510+
511+
image_sample v[5:6], v1, s[8:11], s[12:15] dmask:0x3 dim:SQ_RSRC_IMG_1D
512+
// NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: the RSRC reg should be 256-bit, or the r128 flag is required
513+
514+
image_gather4 v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_1D r128
515+
// NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: r128 not allowed with 256-bit RSRC reg
516+
517+
image_gather4 v[5:8], v[1:2], s[8:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_1D
518+
// NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: the RSRC reg should be 256-bit, or the r128 flag is required

‎llvm/test/MC/AMDGPU/gfx11_asm_mimg_features.s

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -39,9 +39,8 @@ image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D slc
3939
image_load v0, v255, s[0:7] dmask:0x6 dim:SQ_RSRC_IMG_1D d16
4040
// GFX11: image_load v0, v255, s[0:7] dmask:0x6 dim:SQ_RSRC_IMG_1D d16 ; encoding: [0x00,0x06,0x02,0xf0,0xff,0x00,0x00,0x00]
4141

42-
// FIXME: This test is incorrect because r128 assumes a 128-bit SRSRC.
43-
image_load v0, v255, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D r128
44-
// GFX11: image_load v0, v255, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D r128 ; encoding: [0x00,0x81,0x00,0xf0,0xff,0x00,0x00,0x00]
42+
image_load v0, v255, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
43+
// GFX11: image_load v0, v255, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x01,0x00,0xf0,0xff,0x00,0x00,0x00]
4544

4645
image_load v0, v[2:3], s[0:7] dmask:0x1 dim:2D
4746
// GFX11: image_load v0, v[2:3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x04,0x01,0x00,0xf0,0x02,0x00,0x00,0x00]

‎llvm/test/MC/AMDGPU/gfx12_asm_vimage.s

Lines changed: 8 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -111,9 +111,8 @@ image_load v[1:4], [v0, v1], s[16:23] dmask:0xf dim:SQ_RSRC_IMG_2D
111111
image_load v[1:5], [v0, v1], s[16:23] dmask:0xf dim:SQ_RSRC_IMG_2D tfe
112112
// GFX12: encoding: [0x01,0x00,0xc0,0xd3,0x01,0x20,0x80,0x00,0x00,0x01,0x00,0x00]
113113

114-
// FIXME: This test is incorrect because r128 assumes a 128-bit RSRC.
115-
image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D r128
116-
// GFX12: encoding: [0x10,0x00,0x40,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
114+
image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
115+
// GFX12: encoding: [0x00,0x00,0x40,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
117116

118117
image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D scope:SCOPE_CU
119118
// GFX12: encoding: [0x00,0x00,0x40,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
@@ -154,9 +153,8 @@ image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_LOAD_BYPASS scope:S
154153
image_load v[0:2], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY th:TH_LOAD_HT scope:SCOPE_SE a16 tfe d16
155154
// GFX12: encoding: [0x65,0x00,0xc0,0xd3,0x00,0x10,0xa4,0x00,0x04,0x05,0x00,0x00]
156155

157-
// FIXME: This test is incorrect because r128 assumes a 128-bit RSRC.
158-
image_load v[0:2], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY th:TH_LOAD_HT scope:SCOPE_SE r128 a16 tfe d16
159-
// GFX12: encoding: [0x75,0x00,0xc0,0xd3,0x00,0x10,0xa4,0x00,0x04,0x05,0x00,0x00]
156+
image_load v[0:2], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY th:TH_LOAD_HT scope:SCOPE_SE a16 tfe d16
157+
// GFX12: encoding: [0x65,0x00,0xc0,0xd3,0x00,0x10,0xa4,0x00,0x04,0x05,0x00,0x00]
160158

161159
image_load v[4:7], [v1, v0], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D
162160
// GFX12: encoding: [0x01,0x00,0xc0,0xd3,0x04,0x08,0x00,0x00,0x01,0x00,0x00,0x00]
@@ -374,9 +372,8 @@ image_store v[1:4], [v0, v1], s[16:23] dmask:0xf dim:SQ_RSRC_IMG_2D
374372
image_store v[1:5], [v0, v1], s[16:23] dmask:0xf dim:SQ_RSRC_IMG_2D tfe
375373
// GFX12: encoding: [0x01,0x80,0xc1,0xd3,0x01,0x20,0x80,0x00,0x00,0x01,0x00,0x00]
376374

377-
// FIXME: This test is incorrect because r128 assumes a 128-bit RSRC.
378-
image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D r128
379-
// GFX12: encoding: [0x10,0x80,0x41,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
375+
image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
376+
// GFX12: encoding: [0x00,0x80,0x41,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
380377

381378
image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D scope:SCOPE_CU
382379
// GFX12: encoding: [0x00,0x80,0x41,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
@@ -558,9 +555,8 @@ image_atomic_swap v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_CASCA
558555
image_atomic_swap v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_CASCADE_NT scope:SCOPE_SYS
559556
// GFX12: encoding: [0x00,0x80,0x42,0xd0,0x00,0x00,0x6c,0x00,0x00,0x00,0x00,0x00]
560557

561-
// FIXME: This test is incorrect because r128 assumes a 128-bit RSRC.
562-
image_atomic_swap v0, [v2, v3], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D r128
563-
// GFX12: encoding: [0x11,0x80,0x42,0xd0,0x00,0x08,0x00,0x00,0x02,0x03,0x00,0x00]
558+
image_atomic_swap v0, [v2, v3], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
559+
// GFX12: encoding: [0x01,0x80,0x42,0xd0,0x00,0x08,0x00,0x00,0x02,0x03,0x00,0x00]
564560

565561
image_atomic_swap v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D a16
566562
// GFX12: encoding: [0x40,0x80,0x42,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]

‎llvm/test/MC/AMDGPU/gfx12_asm_vsample.s

Lines changed: 6 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -39,9 +39,8 @@ image_sample v[16:19], [v20, v21], s[20:27], s[80:83] dmask:0xf dim:SQ_RSRC_IMG_
3939
image_sample v[22:24], v25, s[24:31], s[76:79] dmask:0xd dim:SQ_RSRC_IMG_1D unorm
4040
// GFX12: encoding: [0x00,0xe0,0x46,0xe7,0x16,0x30,0x00,0x26,0x19,0x00,0x00,0x00]
4141

42-
// FIXME: This test is incorrect because r128 assumes a 128-bit SRSRC.
43-
image_sample v[22:24], v25, s[24:31], s[76:79] dmask:0xd dim:SQ_RSRC_IMG_1D r128
44-
// GFX12: encoding: [0x10,0xc0,0x46,0xe7,0x16,0x30,0x00,0x26,0x19,0x00,0x00,0x00]
42+
image_sample v[22:24], v25, s[24:31], s[76:79] dmask:0xd dim:SQ_RSRC_IMG_1D
43+
// GFX12: encoding: [0x00,0xc0,0x46,0xe7,0x16,0x30,0x00,0x26,0x19,0x00,0x00,0x00]
4544

4645
image_sample v26, [v27, v28], s[28:35], s[72:75] dmask:0x1 dim:SQ_RSRC_IMG_2D scope:SCOPE_CU
4746
// GFX12: encoding: [0x01,0xc0,0x46,0xe4,0x1a,0x38,0x00,0x24,0x1b,0x1c,0x00,0x00]
@@ -94,9 +93,8 @@ image_sample v[34:35], v37, s[36:43], s[64:67] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
9493
image_sample v[34:35], v37, s[36:43], s[64:67] dmask:0x3 dim:SQ_RSRC_IMG_1D lwe
9594
// GFX12: encoding: [0x00,0xc0,0xc6,0xe4,0x22,0x49,0x00,0x20,0x25,0x00,0x00,0x00]
9695

97-
// FIXME: This test is incorrect because r128 assumes a 128-bit SRSRC.
98-
image_sample v[38:39], [v40, v41], s[40:47], s[60:63] dmask:0xc dim:SQ_RSRC_IMG_CUBE unorm th:TH_LOAD_HT scope:SCOPE_DEV r128 a16 tfe lwe d16
99-
// GFX12: encoding: [0x7b,0xe0,0x06,0xe7,0x26,0x51,0x28,0x1e,0x28,0x29,0x00,0x00]
96+
image_sample v[38:39], [v40, v41], s[40:47], s[60:63] dmask:0xc dim:SQ_RSRC_IMG_CUBE unorm th:TH_LOAD_HT scope:SCOPE_DEV a16 tfe lwe d16
97+
// GFX12: encoding: [0x6b,0xe0,0x06,0xe7,0x26,0x51,0x28,0x1e,0x28,0x29,0x00,0x00]
10098

10199
image_sample_d v64, [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
102100
// GFX12: encoding: [0x00,0x00,0x47,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
@@ -461,9 +459,8 @@ image_gather4 v[64:67], [v32, v33], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D
461459
image_gather4 v[0:3], [v4, v5], s[0:7], s[100:103] dmask:0x8 dim:SQ_RSRC_IMG_2D unorm
462460
// GFX12: encoding: [0x01,0xe0,0x0b,0xe6,0x00,0x00,0x00,0x32,0x04,0x05,0x00,0x00]
463461

464-
// FIXME: This test is incorrect because r128 assumes a 128-bit SRSRC.
465-
image_gather4 v[6:9], [v10, v11], s[8:15], s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_2D r128
466-
// GFX12: encoding: [0x11,0xc0,0x4b,0xe4,0x06,0x10,0x00,0x30,0x0a,0x0b,0x00,0x00]
462+
image_gather4 v[6:9], [v10, v11], s[8:15], s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_2D
463+
// GFX12: encoding: [0x01,0xc0,0x4b,0xe4,0x06,0x10,0x00,0x30,0x0a,0x0b,0x00,0x00]
467464

468465
image_gather4 v[12:15], [v16, v17], s[16:23], s[92:95] dmask:0x2 dim:SQ_RSRC_IMG_2D scope:SCOPE_CU
469466
// GFX12: encoding: [0x01,0xc0,0x8b,0xe4,0x0c,0x20,0x00,0x2e,0x10,0x11,0x00,0x00]

‎llvm/test/MC/AMDGPU/gfx8_asm_mimg.s

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1341,8 +1341,8 @@ image_atomic_umax v5, v1, s[8:15] dmask:0x1 unorm lwe
13411341
image_atomic_umax v5, v1, s[8:15] dmask:0x1 unorm da
13421342
// CHECK: [0x00,0x51,0x5c,0xf0,0x01,0x05,0x02,0x00]
13431343

1344-
image_atomic_umax v5, v1, s[8:15] dmask:0x1 r128
1345-
// CHECK: [0x00,0x81,0x5c,0xf0,0x01,0x05,0x02,0x00]
1344+
image_atomic_umax v5, v1, s[8:15] dmask:0x1
1345+
// CHECK: [0x00,0x01,0x5c,0xf0,0x01,0x05,0x02,0x00]
13461346

13471347
image_atomic_and v5, v1, s[8:15] dmask:0x1 unorm
13481348
// CHECK: [0x00,0x11,0x60,0xf0,0x01,0x05,0x02,0x00]

‎llvm/test/MC/AMDGPU/mimg-err.s

Lines changed: 54 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -98,3 +98,57 @@ image_gather4_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x3
9898
// NOGCN: error: invalid image_gather dmask: only one bit must be set
9999
// NOGFX9: error: invalid image_gather dmask: only one bit must be set
100100
// NOGFX90A: :[[@LINE-3]]:{{[0-9]+}}: error: instruction not supported on this GPU
101+
102+
//===----------------------------------------------------------------------===//
103+
// R128
104+
//===----------------------------------------------------------------------===//
105+
106+
image_atomic_add v5, v1, s[8:11] dmask:0x1
107+
// NOGCN: error: the RSRC reg should be 256-bit, or the r128 flag is required
108+
// NOGFX9: error: operands are not valid for this GPU or mode
109+
// NOGFX90A: error: operands are not valid for this GPU or mode
110+
111+
image_atomic_add v5, v1, s[8:15] dmask:0x1 r128
112+
// NOGCN: error: r128 not allowed with 256-bit RSRC reg
113+
// NOGFX9: error: r128 modifier is not supported on this GPU
114+
// NOGFX90A: error: r128 modifier is not supported on this GPU
115+
116+
image_sample v[193:195], v[237:240], s[28:31], s[4:7] dmask:0x3
117+
// NOGCN: error: the RSRC reg should be 256-bit, or the r128 flag is required
118+
// NOGFX9: error: operands are not valid for this GPU or mode
119+
// NOGFX90A: error: operands are not valid for this GPU or mode
120+
121+
image_sample v[193:195], v[237:240], s[28:35], s[4:7] dmask:0x3 r128
122+
// NOGCN: error: r128 not allowed with 256-bit RSRC reg
123+
// NOGFX9: error: r128 modifier is not supported on this GPU
124+
// NOGFX90A: error: r128 modifier is not supported on this GPU
125+
126+
image_gather4 v[5:8], v[1:4], s[8:11], s[12:15] dmask:0x3
127+
// NOGCN: error: the RSRC reg should be 256-bit, or the r128 flag is required
128+
// NOGFX9: error: operands are not valid for this GPU or mode
129+
// NOGFX90A: error: instruction not supported on this GPU
130+
131+
image_gather4 v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x3 r128
132+
// NOGCN: error: r128 not allowed with 256-bit RSRC reg
133+
// NOGFX9: error: r128 modifier is not supported on this GPU
134+
// NOGFX90A: error: instruction not supported on this GPU
135+
136+
image_load v[5:6], v1, s[8:11] dmask:0x1
137+
// NOGCN: error: the RSRC reg should be 256-bit, or the r128 flag is required
138+
// NOGFX9: error: operands are not valid for this GPU or mode
139+
// NOGFX90A: error: operands are not valid for this GPU or mode
140+
141+
image_load v[5:6], v1, s[8:15] dmask:0x1 r128
142+
// NOGCN: error: r128 not allowed with 256-bit RSRC reg
143+
// NOGFX9: error: r128 modifier is not supported on this GPU
144+
// NOGFX90A: error: r128 modifier is not supported on this GPU
145+
146+
image_store v[4:7], v[237:240], s[28:31] dmask:0x7
147+
// NOGCN: error: the RSRC reg should be 256-bit, or the r128 flag is required
148+
// NOGFX9: error: operands are not valid for this GPU or mode
149+
// NOGFX90A: error: operands are not valid for this GPU or mode
150+
151+
image_store v[4:7], v[237:240], s[28:35] dmask:0x7 r128
152+
// NOGCN: error: r128 not allowed with 256-bit RSRC reg
153+
// NOGFX9: error: r128 modifier is not supported on this GPU
154+
// NOGFX90A: error: r128 modifier is not supported on this GPU

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