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[llvm][AArch64][TableGen] Create a ProcessorAlias record (#96249)
... and use it to organize all of the AArch64 CPU aliases.
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‎clang/test/Driver/aarch64-mac-cpus.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,4 +21,4 @@
2121
// EXPLICIT-A11: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "apple-a11"
2222
// EXPLICIT-A7: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "apple-a7"
2323
// EXPLICIT-A14: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "apple-a14"
24-
// EXPLICIT-M1: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "apple-m1"
24+
// EXPLICIT-M1: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "apple-a14"

‎clang/test/Misc/target-invalid-cpu-note.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,11 +5,11 @@
55

66
// RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix AARCH64
77
// AARCH64: error: unknown target CPU 'not-a-cpu'
8-
// AARCH64-NEXT: note: valid target CPU values are: generic, cortex-a35, cortex-a34, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-a725, cortex-r82, cortex-r82ae, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, cortex-x925, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, neoverse-v3, neoverse-v3ae, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx, thunderxt88, thunderxt81, thunderxt83, thunderx2t99, thunderx3t110, tsv110, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-s4, apple-s5, apple-a13, apple-a14, apple-m1, apple-a15, apple-m2, apple-a16, apple-m3, apple-a17, apple-m4, a64fx, carmel, ampere1, ampere1a, ampere1b, oryon-1, cobalt-100, grace{{$}}
8+
// AARCH64-NEXT: note: valid target CPU values are: a64fx, ampere1, ampere1a, ampere1b, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-a7, apple-a8, apple-a9, apple-m1, apple-m2, apple-m3, apple-m4, apple-s4, apple-s5, carmel, cobalt-100, cortex-a34, cortex-a35, cortex-a510, cortex-a520, cortex-a520ae, cortex-a53, cortex-a55, cortex-a57, cortex-a65, cortex-a65ae, cortex-a710, cortex-a715, cortex-a72, cortex-a720, cortex-a720ae, cortex-a725, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-r82, cortex-r82ae, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, cortex-x925, cyclone, exynos-m3, exynos-m4, exynos-m5, falkor, generic, grace, kryo, neoverse-512tvb, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-n3, neoverse-v1, neoverse-v2, neoverse-v3, neoverse-v3ae, oryon-1, saphira, thunderx, thunderx2t99, thunderx3t110, thunderxt81, thunderxt83, thunderxt88, tsv110{{$}}
99

1010
// RUN: not %clang_cc1 -triple arm64--- -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE_AARCH64
1111
// TUNE_AARCH64: error: unknown target CPU 'not-a-cpu'
12-
// TUNE_AARCH64-NEXT: note: valid target CPU values are: generic, cortex-a35, cortex-a34, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-a725, cortex-r82, cortex-r82ae, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, cortex-x925, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, neoverse-v3, neoverse-v3ae, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx, thunderxt88, thunderxt81, thunderxt83, thunderx2t99, thunderx3t110, tsv110, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-s4, apple-s5, apple-a13, apple-a14, apple-m1, apple-a15, apple-m2, apple-a16, apple-m3, apple-a17, apple-m4, a64fx, carmel, ampere1, ampere1a, ampere1b, oryon-1, cobalt-100, grace{{$}}
12+
// TUNE_AARCH64-NEXT: note: valid target CPU values are: a64fx, ampere1, ampere1a, ampere1b, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-a7, apple-a8, apple-a9, apple-m1, apple-m2, apple-m3, apple-m4, apple-s4, apple-s5, carmel, cobalt-100, cortex-a34, cortex-a35, cortex-a510, cortex-a520, cortex-a520ae, cortex-a53, cortex-a55, cortex-a57, cortex-a65, cortex-a65ae, cortex-a710, cortex-a715, cortex-a72, cortex-a720, cortex-a720ae, cortex-a725, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-r82, cortex-r82ae, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, cortex-x925, cyclone, exynos-m3, exynos-m4, exynos-m5, falkor, generic, grace, kryo, neoverse-512tvb, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-n3, neoverse-v1, neoverse-v2, neoverse-v3, neoverse-v3ae, oryon-1, saphira, thunderx, thunderx2t99, thunderx3t110, thunderxt81, thunderxt83, thunderxt88, tsv110{{$}}
1313

1414
// RUN: not %clang_cc1 -triple i386--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix X86
1515
// X86: error: unknown target CPU 'not-a-cpu'

‎llvm/include/llvm/MC/MCSubtargetInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -225,7 +225,7 @@ class MCSubtargetInfo {
225225
}
226226

227227
/// Check whether the CPU string is valid.
228-
bool isCPUStringValid(StringRef CPU) const {
228+
virtual bool isCPUStringValid(StringRef CPU) const {
229229
auto Found = llvm::lower_bound(ProcDesc, CPU);
230230
return Found != ProcDesc.end() && StringRef(Found->Key) == CPU;
231231
}

‎llvm/include/llvm/TargetParser/AArch64TargetParser.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -311,8 +311,8 @@ struct Alias {
311311
StringRef Name;
312312
};
313313

314-
inline constexpr Alias CpuAliases[] = {{"cobalt-100", "neoverse-n2"},
315-
{"grace", "neoverse-v2"}};
314+
#define EMIT_CPU_ALIAS
315+
#include "llvm/TargetParser/AArch64TargetParserDef.inc"
316316

317317
const ExtensionInfo &getExtensionByID(ArchExtKind(ExtID));
318318

‎llvm/lib/Target/AArch64/AArch64Processors.td

Lines changed: 18 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -930,6 +930,12 @@ def ProcessorFeatures {
930930
list<SubtargetFeature> Generic = [FeatureFPARMv8, FeatureNEON, FeatureETE];
931931
}
932932

933+
// Define an alternative name for a given Processor.
934+
class ProcessorAlias<string n, string alias> {
935+
string Name = n;
936+
string Alias = alias;
937+
}
938+
933939
// FeatureFuseAdrpAdd is enabled under Generic to allow linker merging
934940
// optimizations.
935941
def : ProcessorModel<"generic", CortexA510Model, ProcessorFeatures.Generic,
@@ -1005,6 +1011,7 @@ def : ProcessorModel<"neoverse-n1", NeoverseN1Model,
10051011
ProcessorFeatures.NeoverseN1, [TuneNeoverseN1]>;
10061012
def : ProcessorModel<"neoverse-n2", NeoverseN2Model,
10071013
ProcessorFeatures.NeoverseN2, [TuneNeoverseN2]>;
1014+
def : ProcessorAlias<"cobalt-100", "neoverse-n2">;
10081015
def : ProcessorModel<"neoverse-n3", NeoverseN2Model,
10091016
ProcessorFeatures.NeoverseN3, [TuneNeoverseN3]>;
10101017
def : ProcessorModel<"neoverse-512tvb", NeoverseV1Model,
@@ -1013,6 +1020,7 @@ def : ProcessorModel<"neoverse-v1", NeoverseV1Model,
10131020
ProcessorFeatures.NeoverseV1, [TuneNeoverseV1]>;
10141021
def : ProcessorModel<"neoverse-v2", NeoverseV2Model,
10151022
ProcessorFeatures.NeoverseV2, [TuneNeoverseV2]>;
1023+
def : ProcessorAlias<"grace", "neoverse-v2">;
10161024
def : ProcessorModel<"neoverse-v3", NeoverseV2Model,
10171025
ProcessorFeatures.NeoverseV3, [TuneNeoverseV3]>;
10181026
def : ProcessorModel<"neoverse-v3ae", NeoverseV2Model,
@@ -1050,15 +1058,12 @@ def : ProcessorModel<"tsv110", TSV110Model, ProcessorFeatures.TSV110,
10501058

10511059
// Apple CPUs
10521060

1053-
// Support cyclone as an alias for apple-a7 so we can still LTO old bitcode.
1054-
def : ProcessorModel<"cyclone", CycloneModel, ProcessorFeatures.AppleA7,
1055-
[TuneAppleA7]>;
10561061
def : ProcessorModel<"apple-a7", CycloneModel, ProcessorFeatures.AppleA7,
10571062
[TuneAppleA7]>;
1058-
def : ProcessorModel<"apple-a8", CycloneModel, ProcessorFeatures.AppleA7,
1059-
[TuneAppleA7]>;
1060-
def : ProcessorModel<"apple-a9", CycloneModel, ProcessorFeatures.AppleA7,
1061-
[TuneAppleA7]>;
1063+
// Support cyclone as an alias for apple-a7 so we can still LTO old bitcode.
1064+
def : ProcessorAlias<"cyclone", "apple-a7">;
1065+
def : ProcessorAlias<"apple-a8", "apple-a7">;
1066+
def : ProcessorAlias<"apple-a9", "apple-a7">;
10621067

10631068
def : ProcessorModel<"apple-a10", CycloneModel, ProcessorFeatures.AppleA10,
10641069
[TuneAppleA10]>;
@@ -1068,28 +1073,23 @@ def : ProcessorModel<"apple-a11", CycloneModel, ProcessorFeatures.AppleA11,
10681073

10691074
def : ProcessorModel<"apple-a12", CycloneModel, ProcessorFeatures.AppleA12,
10701075
[TuneAppleA12]>;
1071-
def : ProcessorModel<"apple-s4", CycloneModel, ProcessorFeatures.AppleA12,
1072-
[TuneAppleA12]>;
1073-
def : ProcessorModel<"apple-s5", CycloneModel, ProcessorFeatures.AppleA12,
1074-
[TuneAppleA12]>;
1076+
def : ProcessorAlias<"apple-s4", "apple-a12">;
1077+
def : ProcessorAlias<"apple-s5", "apple-a12">;
10751078

10761079
def : ProcessorModel<"apple-a13", CycloneModel, ProcessorFeatures.AppleA13,
10771080
[TuneAppleA13]>;
10781081

10791082
def : ProcessorModel<"apple-a14", CycloneModel, ProcessorFeatures.AppleA14,
10801083
[TuneAppleA14]>;
1081-
def : ProcessorModel<"apple-m1", CycloneModel, ProcessorFeatures.AppleA14,
1082-
[TuneAppleA14]>;
1084+
def : ProcessorAlias<"apple-m1", "apple-a14">;
10831085

10841086
def : ProcessorModel<"apple-a15", CycloneModel, ProcessorFeatures.AppleA15,
10851087
[TuneAppleA15]>;
1086-
def : ProcessorModel<"apple-m2", CycloneModel, ProcessorFeatures.AppleA15,
1087-
[TuneAppleA15]>;
1088+
def : ProcessorAlias<"apple-m2", "apple-a15">;
10881089

10891090
def : ProcessorModel<"apple-a16", CycloneModel, ProcessorFeatures.AppleA16,
10901091
[TuneAppleA16]>;
1091-
def : ProcessorModel<"apple-m3", CycloneModel, ProcessorFeatures.AppleA16,
1092-
[TuneAppleA16]>;
1092+
def : ProcessorAlias<"apple-m3", "apple-a16">;
10931093

10941094
def : ProcessorModel<"apple-a17", CycloneModel, ProcessorFeatures.AppleA17,
10951095
[TuneAppleA17]>;
@@ -1098,8 +1098,7 @@ def : ProcessorModel<"apple-m4", CycloneModel, ProcessorFeatures.AppleM4,
10981098
[TuneAppleM4]>;
10991099

11001100
// Alias for the latest Apple processor model supported by LLVM.
1101-
def : ProcessorModel<"apple-latest", CycloneModel, ProcessorFeatures.AppleM4,
1102-
[TuneAppleM4]>;
1101+
def : ProcessorAlias<"apple-latest", "apple-m4">;
11031102

11041103

11051104
// Fujitsu A64FX

‎llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,7 @@
2929
#include "llvm/MC/TargetRegistry.h"
3030
#include "llvm/Support/Endian.h"
3131
#include "llvm/Support/ErrorHandling.h"
32+
#include "llvm/TargetParser/AArch64TargetParser.h"
3233

3334
using namespace llvm;
3435

@@ -51,6 +52,8 @@ static MCInstrInfo *createAArch64MCInstrInfo() {
5152

5253
static MCSubtargetInfo *
5354
createAArch64MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
55+
CPU = AArch64::resolveCPUAlias(CPU);
56+
5457
if (CPU.empty()) {
5558
CPU = "generic";
5659
if (FS.empty())

‎llvm/lib/TargetParser/AArch64TargetParser.cpp

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -89,10 +89,14 @@ StringRef AArch64::getArchExtFeature(StringRef ArchExt) {
8989

9090
void AArch64::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values) {
9191
for (const auto &C : CpuInfos)
92-
Values.push_back(C.Name);
92+
Values.push_back(C.Name);
9393

9494
for (const auto &Alias : CpuAliases)
95-
Values.push_back(Alias.AltName);
95+
// The apple-latest alias is backend only, do not expose it to clang's -mcpu.
96+
if (Alias.AltName != "apple-latest")
97+
Values.push_back(Alias.AltName);
98+
99+
llvm::sort(Values);
96100
}
97101

98102
bool AArch64::isX18ReservedByDefault(const Triple &TT) {

‎llvm/utils/TableGen/ARMTargetDefEmitter.cpp

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,7 @@
1414

1515
#include "llvm/ADT/StringSet.h"
1616
#include "llvm/Support/Format.h"
17+
#include "llvm/Support/FormatVariadic.h"
1718
#include "llvm/TableGen/Error.h"
1819
#include "llvm/TableGen/Record.h"
1920
#include "llvm/TableGen/TableGenBackend.h"
@@ -219,6 +220,36 @@ static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream &OS) {
219220
<< "#endif // EMIT_ARCHITECTURES\n"
220221
<< "\n";
221222

223+
// Emit CPU Aliases
224+
OS << "#ifdef EMIT_CPU_ALIAS\n"
225+
<< "inline constexpr Alias CpuAliases[] = {\n";
226+
227+
llvm::StringSet<> Processors;
228+
for (const Record *Rec : RK.getAllDerivedDefinitions("ProcessorModel"))
229+
Processors.insert(Rec->getValueAsString("Name"));
230+
231+
llvm::StringSet<> Aliases;
232+
for (const Record *Rec : RK.getAllDerivedDefinitions("ProcessorAlias")) {
233+
auto Name = Rec->getValueAsString("Name");
234+
auto Alias = Rec->getValueAsString("Alias");
235+
if (!Processors.contains(Alias))
236+
PrintFatalError(
237+
Rec, "Alias '" + Name + "' references a non-existent ProcessorModel '" + Alias + "'");
238+
if (Processors.contains(Name))
239+
PrintFatalError(
240+
Rec, "Alias '" + Name + "' duplicates an existing ProcessorModel");
241+
if (!Aliases.insert(Name).second)
242+
PrintFatalError(
243+
Rec, "Alias '" + Name + "' duplicates an existing ProcessorAlias");
244+
245+
OS << llvm::formatv(R"( { "{0}", "{1}" },)", Name, Alias) << '\n';
246+
}
247+
248+
OS << "};\n"
249+
<< "#undef EMIT_CPU_ALIAS\n"
250+
<< "#endif // EMIT_CPU_ALIAS\n"
251+
<< "\n";
252+
222253
// Emit CPU information
223254
OS << "#ifdef EMIT_CPU_INFO\n"
224255
<< "inline constexpr CpuInfo CpuInfos[] = {\n";

‎llvm/utils/TableGen/SubtargetEmitter.cpp

Lines changed: 24 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -239,6 +239,9 @@ void SubtargetEmitter::EmitSubtargetInfoMacroCalls(raw_ostream &OS) {
239239

240240
OS << "\n#ifdef GET_SUBTARGETINFO_MC_DESC\n";
241241
OS << "#undef GET_SUBTARGETINFO_MC_DESC\n\n";
242+
243+
if (Target == "AArch64")
244+
OS << "#include \"llvm/TargetParser/AArch64TargetParser.h\"\n\n";
242245
}
243246

244247
//
@@ -1895,6 +1898,10 @@ void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS) {
18951898
return;
18961899
}
18971900

1901+
if (Target == "AArch64")
1902+
OS << " CPU = AArch64::resolveCPUAlias(CPU);\n"
1903+
<< " TuneCPU = AArch64::resolveCPUAlias(TuneCPU);\n";
1904+
18981905
OS << " InitMCProcessorInfo(CPU, TuneCPU, FS);\n"
18991906
<< " const FeatureBitset &Bits = getFeatureBits();\n";
19001907

@@ -1946,6 +1953,11 @@ void SubtargetEmitter::emitGenMCSubtargetInfo(raw_ostream &OS) {
19461953
OS << " unsigned getHwMode(enum HwModeType type = HwMode_Default) const "
19471954
"override;\n";
19481955
}
1956+
if (Target == "AArch64")
1957+
OS << " bool isCPUStringValid(StringRef CPU) const override {\n"
1958+
<< " CPU = AArch64::resolveCPUAlias(CPU);\n"
1959+
<< " return MCSubtargetInfo::isCPUStringValid(CPU);\n"
1960+
<< " }\n";
19491961
OS << "};\n";
19501962
EmitHwModeCheck(Target + "GenMCSubtargetInfo", OS);
19511963
}
@@ -2013,6 +2025,9 @@ void SubtargetEmitter::run(raw_ostream &OS) {
20132025
OS << "\nstatic inline MCSubtargetInfo *create" << Target
20142026
<< "MCSubtargetInfoImpl("
20152027
<< "const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {\n";
2028+
if (Target == "AArch64")
2029+
OS << " CPU = AArch64::resolveCPUAlias(CPU);\n"
2030+
<< " TuneCPU = AArch64::resolveCPUAlias(TuneCPU);\n";
20162031
OS << " return new " << Target
20172032
<< "GenMCSubtargetInfo(TT, CPU, TuneCPU, FS, ";
20182033
if (NumFeatures)
@@ -2045,6 +2060,8 @@ void SubtargetEmitter::run(raw_ostream &OS) {
20452060

20462061
OS << "#include \"llvm/Support/Debug.h\"\n";
20472062
OS << "#include \"llvm/Support/raw_ostream.h\"\n\n";
2063+
if (Target == "AArch64")
2064+
OS << "#include \"llvm/TargetParser/AArch64TargetParser.h\"\n\n";
20482065
ParseFeaturesFunction(OS);
20492066

20502067
OS << "#endif // GET_SUBTARGETINFO_TARGET_DESC\n\n";
@@ -2112,8 +2129,13 @@ void SubtargetEmitter::run(raw_ostream &OS) {
21122129
}
21132130

21142131
OS << ClassName << "::" << ClassName << "(const Triple &TT, StringRef CPU, "
2115-
<< "StringRef TuneCPU, StringRef FS)\n"
2116-
<< " : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ";
2132+
<< "StringRef TuneCPU, StringRef FS)\n";
2133+
2134+
if (Target == "AArch64")
2135+
OS << " : TargetSubtargetInfo(TT, AArch64::resolveCPUAlias(CPU),\n"
2136+
<< " AArch64::resolveCPUAlias(TuneCPU), FS, ";
2137+
else
2138+
OS << " : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ";
21172139
if (NumFeatures)
21182140
OS << "ArrayRef(" << Target << "FeatureKV, " << NumFeatures << "), ";
21192141
else

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