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lukel97lukel97
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[RISCV] Remove -riscv-v-vector-bits-max from reverse tests. NFC
There doesn't seem to be any difference in the output anymore between the options.
1 parent 698b42c commit 5cdd204

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+60
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‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll

Lines changed: 60 additions & 186 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,NO-ZVBB,RV32-BITS-UNKNOWN
3-
; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zfh,+zvfh -riscv-v-vector-bits-max=256 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,NO-ZVBB,RV32-BITS-256
4-
; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zfh,+zvfh -riscv-v-vector-bits-max=512 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,NO-ZVBB,RV32-BITS-512
5-
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,NO-ZVBB,RV64-BITS-UNKNOWN
6-
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfh,+zvfh -riscv-v-vector-bits-max=256 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,NO-ZVBB,RV64-BITS-256
7-
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfh,+zvfh -riscv-v-vector-bits-max=512 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,NO-ZVBB,RV64-BITS-512
2+
; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,NO-ZVBB,RV32
3+
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,NO-ZVBB,RV64
84
; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zfh,+zvfh,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVBB,RV32-ZVBB
95
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfh,+zvfh,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVBB,RV64-ZVBB
106

@@ -648,65 +644,25 @@ define <8 x double> @reverse_v8f64(<8 x double> %a) {
648644

649645

650646
define <3 x i64> @reverse_v3i64(<3 x i64> %a) {
651-
; RV32-BITS-UNKNOWN-LABEL: reverse_v3i64:
652-
; RV32-BITS-UNKNOWN: # %bb.0:
653-
; RV32-BITS-UNKNOWN-NEXT: lui a0, %hi(.LCPI44_0)
654-
; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, %lo(.LCPI44_0)
655-
; RV32-BITS-UNKNOWN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
656-
; RV32-BITS-UNKNOWN-NEXT: vle16.v v12, (a0)
657-
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v12
658-
; RV32-BITS-UNKNOWN-NEXT: vmv.v.v v8, v10
659-
; RV32-BITS-UNKNOWN-NEXT: ret
660-
;
661-
; RV32-BITS-256-LABEL: reverse_v3i64:
662-
; RV32-BITS-256: # %bb.0:
663-
; RV32-BITS-256-NEXT: lui a0, %hi(.LCPI44_0)
664-
; RV32-BITS-256-NEXT: addi a0, a0, %lo(.LCPI44_0)
665-
; RV32-BITS-256-NEXT: vsetivli zero, 8, e32, m2, ta, ma
666-
; RV32-BITS-256-NEXT: vle16.v v12, (a0)
667-
; RV32-BITS-256-NEXT: vrgatherei16.vv v10, v8, v12
668-
; RV32-BITS-256-NEXT: vmv.v.v v8, v10
669-
; RV32-BITS-256-NEXT: ret
670-
;
671-
; RV32-BITS-512-LABEL: reverse_v3i64:
672-
; RV32-BITS-512: # %bb.0:
673-
; RV32-BITS-512-NEXT: lui a0, %hi(.LCPI44_0)
674-
; RV32-BITS-512-NEXT: addi a0, a0, %lo(.LCPI44_0)
675-
; RV32-BITS-512-NEXT: vsetivli zero, 8, e32, m2, ta, ma
676-
; RV32-BITS-512-NEXT: vle16.v v12, (a0)
677-
; RV32-BITS-512-NEXT: vrgatherei16.vv v10, v8, v12
678-
; RV32-BITS-512-NEXT: vmv.v.v v8, v10
679-
; RV32-BITS-512-NEXT: ret
680-
;
681-
; RV64-BITS-UNKNOWN-LABEL: reverse_v3i64:
682-
; RV64-BITS-UNKNOWN: # %bb.0:
683-
; RV64-BITS-UNKNOWN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
684-
; RV64-BITS-UNKNOWN-NEXT: vid.v v10
685-
; RV64-BITS-UNKNOWN-NEXT: vrsub.vi v12, v10, 2
686-
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e64, m2, ta, ma
687-
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v12
688-
; RV64-BITS-UNKNOWN-NEXT: vmv.v.v v8, v10
689-
; RV64-BITS-UNKNOWN-NEXT: ret
690-
;
691-
; RV64-BITS-256-LABEL: reverse_v3i64:
692-
; RV64-BITS-256: # %bb.0:
693-
; RV64-BITS-256-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
694-
; RV64-BITS-256-NEXT: vid.v v10
695-
; RV64-BITS-256-NEXT: vrsub.vi v12, v10, 2
696-
; RV64-BITS-256-NEXT: vsetvli zero, zero, e64, m2, ta, ma
697-
; RV64-BITS-256-NEXT: vrgatherei16.vv v10, v8, v12
698-
; RV64-BITS-256-NEXT: vmv.v.v v8, v10
699-
; RV64-BITS-256-NEXT: ret
700-
;
701-
; RV64-BITS-512-LABEL: reverse_v3i64:
702-
; RV64-BITS-512: # %bb.0:
703-
; RV64-BITS-512-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
704-
; RV64-BITS-512-NEXT: vid.v v10
705-
; RV64-BITS-512-NEXT: vrsub.vi v12, v10, 2
706-
; RV64-BITS-512-NEXT: vsetvli zero, zero, e64, m2, ta, ma
707-
; RV64-BITS-512-NEXT: vrgatherei16.vv v10, v8, v12
708-
; RV64-BITS-512-NEXT: vmv.v.v v8, v10
709-
; RV64-BITS-512-NEXT: ret
647+
; RV32-LABEL: reverse_v3i64:
648+
; RV32: # %bb.0:
649+
; RV32-NEXT: lui a0, %hi(.LCPI44_0)
650+
; RV32-NEXT: addi a0, a0, %lo(.LCPI44_0)
651+
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
652+
; RV32-NEXT: vle16.v v12, (a0)
653+
; RV32-NEXT: vrgatherei16.vv v10, v8, v12
654+
; RV32-NEXT: vmv.v.v v8, v10
655+
; RV32-NEXT: ret
656+
;
657+
; RV64-LABEL: reverse_v3i64:
658+
; RV64: # %bb.0:
659+
; RV64-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
660+
; RV64-NEXT: vid.v v10
661+
; RV64-NEXT: vrsub.vi v12, v10, 2
662+
; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma
663+
; RV64-NEXT: vrgatherei16.vv v10, v8, v12
664+
; RV64-NEXT: vmv.v.v v8, v10
665+
; RV64-NEXT: ret
710666
;
711667
; RV32-ZVBB-LABEL: reverse_v3i64:
712668
; RV32-ZVBB: # %bb.0:
@@ -732,65 +688,25 @@ define <3 x i64> @reverse_v3i64(<3 x i64> %a) {
732688
}
733689

734690
define <6 x i64> @reverse_v6i64(<6 x i64> %a) {
735-
; RV32-BITS-UNKNOWN-LABEL: reverse_v6i64:
736-
; RV32-BITS-UNKNOWN: # %bb.0:
737-
; RV32-BITS-UNKNOWN-NEXT: lui a0, %hi(.LCPI45_0)
738-
; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, %lo(.LCPI45_0)
739-
; RV32-BITS-UNKNOWN-NEXT: vsetivli zero, 16, e32, m4, ta, ma
740-
; RV32-BITS-UNKNOWN-NEXT: vle16.v v16, (a0)
741-
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v12, v8, v16
742-
; RV32-BITS-UNKNOWN-NEXT: vmv.v.v v8, v12
743-
; RV32-BITS-UNKNOWN-NEXT: ret
744-
;
745-
; RV32-BITS-256-LABEL: reverse_v6i64:
746-
; RV32-BITS-256: # %bb.0:
747-
; RV32-BITS-256-NEXT: lui a0, %hi(.LCPI45_0)
748-
; RV32-BITS-256-NEXT: addi a0, a0, %lo(.LCPI45_0)
749-
; RV32-BITS-256-NEXT: vsetivli zero, 16, e32, m4, ta, ma
750-
; RV32-BITS-256-NEXT: vle16.v v16, (a0)
751-
; RV32-BITS-256-NEXT: vrgatherei16.vv v12, v8, v16
752-
; RV32-BITS-256-NEXT: vmv.v.v v8, v12
753-
; RV32-BITS-256-NEXT: ret
754-
;
755-
; RV32-BITS-512-LABEL: reverse_v6i64:
756-
; RV32-BITS-512: # %bb.0:
757-
; RV32-BITS-512-NEXT: lui a0, %hi(.LCPI45_0)
758-
; RV32-BITS-512-NEXT: addi a0, a0, %lo(.LCPI45_0)
759-
; RV32-BITS-512-NEXT: vsetivli zero, 16, e32, m4, ta, ma
760-
; RV32-BITS-512-NEXT: vle16.v v16, (a0)
761-
; RV32-BITS-512-NEXT: vrgatherei16.vv v12, v8, v16
762-
; RV32-BITS-512-NEXT: vmv.v.v v8, v12
763-
; RV32-BITS-512-NEXT: ret
764-
;
765-
; RV64-BITS-UNKNOWN-LABEL: reverse_v6i64:
766-
; RV64-BITS-UNKNOWN: # %bb.0:
767-
; RV64-BITS-UNKNOWN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
768-
; RV64-BITS-UNKNOWN-NEXT: vid.v v12
769-
; RV64-BITS-UNKNOWN-NEXT: vrsub.vi v16, v12, 5
770-
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e64, m4, ta, ma
771-
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v12, v8, v16
772-
; RV64-BITS-UNKNOWN-NEXT: vmv.v.v v8, v12
773-
; RV64-BITS-UNKNOWN-NEXT: ret
774-
;
775-
; RV64-BITS-256-LABEL: reverse_v6i64:
776-
; RV64-BITS-256: # %bb.0:
777-
; RV64-BITS-256-NEXT: vsetivli zero, 8, e16, m1, ta, ma
778-
; RV64-BITS-256-NEXT: vid.v v12
779-
; RV64-BITS-256-NEXT: vrsub.vi v16, v12, 5
780-
; RV64-BITS-256-NEXT: vsetvli zero, zero, e64, m4, ta, ma
781-
; RV64-BITS-256-NEXT: vrgatherei16.vv v12, v8, v16
782-
; RV64-BITS-256-NEXT: vmv.v.v v8, v12
783-
; RV64-BITS-256-NEXT: ret
784-
;
785-
; RV64-BITS-512-LABEL: reverse_v6i64:
786-
; RV64-BITS-512: # %bb.0:
787-
; RV64-BITS-512-NEXT: vsetivli zero, 8, e16, m1, ta, ma
788-
; RV64-BITS-512-NEXT: vid.v v12
789-
; RV64-BITS-512-NEXT: vrsub.vi v16, v12, 5
790-
; RV64-BITS-512-NEXT: vsetvli zero, zero, e64, m4, ta, ma
791-
; RV64-BITS-512-NEXT: vrgatherei16.vv v12, v8, v16
792-
; RV64-BITS-512-NEXT: vmv.v.v v8, v12
793-
; RV64-BITS-512-NEXT: ret
691+
; RV32-LABEL: reverse_v6i64:
692+
; RV32: # %bb.0:
693+
; RV32-NEXT: lui a0, %hi(.LCPI45_0)
694+
; RV32-NEXT: addi a0, a0, %lo(.LCPI45_0)
695+
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
696+
; RV32-NEXT: vle16.v v16, (a0)
697+
; RV32-NEXT: vrgatherei16.vv v12, v8, v16
698+
; RV32-NEXT: vmv.v.v v8, v12
699+
; RV32-NEXT: ret
700+
;
701+
; RV64-LABEL: reverse_v6i64:
702+
; RV64: # %bb.0:
703+
; RV64-NEXT: vsetivli zero, 8, e16, m1, ta, ma
704+
; RV64-NEXT: vid.v v12
705+
; RV64-NEXT: vrsub.vi v16, v12, 5
706+
; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, ma
707+
; RV64-NEXT: vrgatherei16.vv v12, v8, v16
708+
; RV64-NEXT: vmv.v.v v8, v12
709+
; RV64-NEXT: ret
794710
;
795711
; RV32-ZVBB-LABEL: reverse_v6i64:
796712
; RV32-ZVBB: # %bb.0:
@@ -816,68 +732,26 @@ define <6 x i64> @reverse_v6i64(<6 x i64> %a) {
816732
}
817733

818734
define <12 x i64> @reverse_v12i64(<12 x i64> %a) {
819-
; RV32-BITS-UNKNOWN-LABEL: reverse_v12i64:
820-
; RV32-BITS-UNKNOWN: # %bb.0:
821-
; RV32-BITS-UNKNOWN-NEXT: li a0, 32
822-
; RV32-BITS-UNKNOWN-NEXT: lui a1, %hi(.LCPI46_0)
823-
; RV32-BITS-UNKNOWN-NEXT: addi a1, a1, %lo(.LCPI46_0)
824-
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
825-
; RV32-BITS-UNKNOWN-NEXT: vle16.v v24, (a1)
826-
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v16, v8, v24
827-
; RV32-BITS-UNKNOWN-NEXT: vmv.v.v v8, v16
828-
; RV32-BITS-UNKNOWN-NEXT: ret
829-
;
830-
; RV32-BITS-256-LABEL: reverse_v12i64:
831-
; RV32-BITS-256: # %bb.0:
832-
; RV32-BITS-256-NEXT: li a0, 32
833-
; RV32-BITS-256-NEXT: lui a1, %hi(.LCPI46_0)
834-
; RV32-BITS-256-NEXT: addi a1, a1, %lo(.LCPI46_0)
835-
; RV32-BITS-256-NEXT: vsetvli zero, a0, e32, m8, ta, ma
836-
; RV32-BITS-256-NEXT: vle16.v v24, (a1)
837-
; RV32-BITS-256-NEXT: vrgatherei16.vv v16, v8, v24
838-
; RV32-BITS-256-NEXT: vmv.v.v v8, v16
839-
; RV32-BITS-256-NEXT: ret
840-
;
841-
; RV32-BITS-512-LABEL: reverse_v12i64:
842-
; RV32-BITS-512: # %bb.0:
843-
; RV32-BITS-512-NEXT: li a0, 32
844-
; RV32-BITS-512-NEXT: lui a1, %hi(.LCPI46_0)
845-
; RV32-BITS-512-NEXT: addi a1, a1, %lo(.LCPI46_0)
846-
; RV32-BITS-512-NEXT: vsetvli zero, a0, e32, m8, ta, ma
847-
; RV32-BITS-512-NEXT: vle16.v v24, (a1)
848-
; RV32-BITS-512-NEXT: vrgatherei16.vv v16, v8, v24
849-
; RV32-BITS-512-NEXT: vmv.v.v v8, v16
850-
; RV32-BITS-512-NEXT: ret
851-
;
852-
; RV64-BITS-UNKNOWN-LABEL: reverse_v12i64:
853-
; RV64-BITS-UNKNOWN: # %bb.0:
854-
; RV64-BITS-UNKNOWN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
855-
; RV64-BITS-UNKNOWN-NEXT: vid.v v16
856-
; RV64-BITS-UNKNOWN-NEXT: vrsub.vi v24, v16, 11
857-
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e64, m8, ta, ma
858-
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v16, v8, v24
859-
; RV64-BITS-UNKNOWN-NEXT: vmv.v.v v8, v16
860-
; RV64-BITS-UNKNOWN-NEXT: ret
861-
;
862-
; RV64-BITS-256-LABEL: reverse_v12i64:
863-
; RV64-BITS-256: # %bb.0:
864-
; RV64-BITS-256-NEXT: vsetivli zero, 16, e16, m2, ta, ma
865-
; RV64-BITS-256-NEXT: vid.v v16
866-
; RV64-BITS-256-NEXT: vrsub.vi v24, v16, 11
867-
; RV64-BITS-256-NEXT: vsetvli zero, zero, e64, m8, ta, ma
868-
; RV64-BITS-256-NEXT: vrgatherei16.vv v16, v8, v24
869-
; RV64-BITS-256-NEXT: vmv.v.v v8, v16
870-
; RV64-BITS-256-NEXT: ret
871-
;
872-
; RV64-BITS-512-LABEL: reverse_v12i64:
873-
; RV64-BITS-512: # %bb.0:
874-
; RV64-BITS-512-NEXT: vsetivli zero, 16, e16, m2, ta, ma
875-
; RV64-BITS-512-NEXT: vid.v v16
876-
; RV64-BITS-512-NEXT: vrsub.vi v24, v16, 11
877-
; RV64-BITS-512-NEXT: vsetvli zero, zero, e64, m8, ta, ma
878-
; RV64-BITS-512-NEXT: vrgatherei16.vv v16, v8, v24
879-
; RV64-BITS-512-NEXT: vmv.v.v v8, v16
880-
; RV64-BITS-512-NEXT: ret
735+
; RV32-LABEL: reverse_v12i64:
736+
; RV32: # %bb.0:
737+
; RV32-NEXT: li a0, 32
738+
; RV32-NEXT: lui a1, %hi(.LCPI46_0)
739+
; RV32-NEXT: addi a1, a1, %lo(.LCPI46_0)
740+
; RV32-NEXT: vsetvli zero, a0, e32, m8, ta, ma
741+
; RV32-NEXT: vle16.v v24, (a1)
742+
; RV32-NEXT: vrgatherei16.vv v16, v8, v24
743+
; RV32-NEXT: vmv.v.v v8, v16
744+
; RV32-NEXT: ret
745+
;
746+
; RV64-LABEL: reverse_v12i64:
747+
; RV64: # %bb.0:
748+
; RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma
749+
; RV64-NEXT: vid.v v16
750+
; RV64-NEXT: vrsub.vi v24, v16, 11
751+
; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
752+
; RV64-NEXT: vrgatherei16.vv v16, v8, v24
753+
; RV64-NEXT: vmv.v.v v8, v16
754+
; RV64-NEXT: ret
881755
;
882756
; RV32-ZVBB-LABEL: reverse_v12i64:
883757
; RV32-ZVBB: # %bb.0:

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