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[RISCV] Add shlcofideleg extension (#141572)
This is for `shlcofideleg` extension, that supports delegating LCOFI interrupts to VS-mode. Spec: https://github.com/riscv/riscv-isa-manual/blob/main/src/hypervisor.adoc
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‎clang/test/Driver/print-supported-extensions-riscv.c

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// CHECK-NEXT: sha 1.0 'Sha' (Augmented Hypervisor)
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// CHECK-NEXT: shcounterenw 1.0 'Shcounterenw' (Support writeable hcounteren enable bit for any hpmcounter that is not read-only zero)
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// CHECK-NEXT: shgatpa 1.0 'Shgatpa' (SvNNx4 mode supported for all modes supported by satp, as well as Bare)
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// CHECK-NEXT: shlcofideleg 1.0 'Shlcofideleg' (Delegating LCOFI Interrupts to VS-mode)
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// CHECK-NEXT: shtvala 1.0 'Shtvala' (htval provides all needed values)
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// CHECK-NEXT: shvsatpa 1.0 'Shvsatpa' (vsatp supports all modes supported by satp)
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// CHECK-NEXT: shvstvala 1.0 'Shvstvala' (vstval provides all needed values)

‎clang/test/Preprocessor/riscv-target-features.c

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// CHECK-NOT: __riscv_sha {{.*$}}
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// CHECK-NOT: __riscv_shcounterenw {{.*$}}
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// CHECK-NOT: __riscv_shgatpa {{.*$}}
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// CHECK-NOT: __riscv_shlcofideleg {{.*$}}
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// CHECK-NOT: __riscv_shtvala {{.*$}}
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// CHECK-NOT: __riscv_shvsatpa {{.*$}}
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// CHECK-NOT: __riscv_shvstvala {{.*$}}
@@ -370,6 +371,14 @@
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// RUN: -o - | FileCheck --check-prefix=CHECK-SHGATPA-EXT %s
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// CHECK-SHGATPA-EXT: __riscv_shgatpa 1000000{{$}}
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// RUN: %clang --target=riscv32-unknown-linux-gnu \
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// RUN: -march=rv32ishlcofideleg -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-SHLCOFIDELEG-EXT %s
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// RUN: %clang --target=riscv64-unknown-linux-gnu \
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// RUN: -march=rv64ishlcofideleg -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-SHLCOFIDELEG-EXT %s
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// CHECK-SHLCOFIDELEG-EXT: __riscv_shlcofideleg 1000000{{$}}
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// RUN: %clang --target=riscv32-unknown-linux-gnu \
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// RUN: -march=rv32ishtvala -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-SHTVALA-EXT %s

‎llvm/docs/RISCVUsage.rst

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@@ -123,6 +123,7 @@ on support follow.
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``Sha`` Supported
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``Shcounterenw`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
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``Shgatpa`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
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``Shlcofideleg`` Supported
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``Shtvala`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
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``Shvsatpa`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
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``Shvstvala`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)

‎llvm/docs/ReleaseNotes.md

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@@ -201,6 +201,7 @@ Changes to the RISC-V Backend
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* Adds experimental assembler support for the SiFive Xsfmm* Attached Matrix
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Extensions.
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* `-mcpu=andes-a25` and `-mcpu=andes-ax25` were added.
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* The `Shlcofideleg` extension was added.
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Changes to the WebAssembly Backend
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----------------------------------

‎llvm/lib/Target/RISCV/RISCVFeatures.td

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@@ -906,6 +906,10 @@ def FeatureStdExtShvsatpa
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: RISCVExtension<1, 0,
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"vsatp supports all modes supported by satp">;
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def FeatureStdExtShlcofideleg
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: RISCVExtension<1, 0,
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"Delegating LCOFI Interrupts to VS-mode">;
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def FeatureStdExtSmaia
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: RISCVExtension<1, 0,
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"Advanced Interrupt Architecture Machine Level">;

‎llvm/test/CodeGen/RISCV/attributes.ll

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; RUN: llc -mtriple=riscv32 -mattr=+shcounterenw %s -o - | FileCheck --check-prefixes=CHECK,RV32SHCOUNTERENW %s
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; RUN: llc -mtriple=riscv32 -mattr=+shgatpa %s -o - | FileCheck --check-prefixes=CHECK,RV32SHGATPA %s
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; RUN: llc -mtriple=riscv32 -mattr=+shvsatpa %s -o - | FileCheck --check-prefixes=CHECK,RV32SHVSATPA %s
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; RUN: llc -mtriple=riscv32 -mattr=+shlcofideleg %s -o - | FileCheck --check-prefixes=CHECK,RV32SHLCOFIDELEG %s
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; RUN: llc -mtriple=riscv32 -mattr=+ssccfg %s -o - | FileCheck --check-prefixes=CHECK,RV32SSCCFG %s
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; RUN: llc -mtriple=riscv32 -mattr=+ssccptr %s -o - | FileCheck --check-prefixes=CHECK,RV32SSCCPTR %s
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; RUN: llc -mtriple=riscv32 -mattr=+sscofpmf %s -o - | FileCheck --check-prefixes=CHECK,RV32SSCOFPMF %s
@@ -222,6 +223,7 @@
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; RUN: llc -mtriple=riscv64 -mattr=+shcounterenw %s -o - | FileCheck --check-prefixes=CHECK,RV64SHCOUNTERENW %s
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; RUN: llc -mtriple=riscv64 -mattr=+shgatpa %s -o - | FileCheck --check-prefixes=CHECK,RV64SHGATPA %s
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; RUN: llc -mtriple=riscv64 -mattr=+shvsatpa %s -o - | FileCheck --check-prefixes=CHECK,RV64SHVSATPA %s
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; RUN: llc -mtriple=riscv64 -mattr=+shlcofideleg %s -o - | FileCheck --check-prefixes=CHECK,RV64SHLCOFIDELEG %s
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; RUN: llc -mtriple=riscv64 -mattr=+ssccfg %s -o - | FileCheck --check-prefixes=CHECK,RV64SSCCFG %s
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; RUN: llc -mtriple=riscv64 -mattr=+ssccptr %s -o - | FileCheck --check-prefixes=CHECK,RV64SSCCPTR %s
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; RUN: llc -mtriple=riscv64 -mattr=+sscofpmf %s -o - | FileCheck --check-prefixes=CHECK,RV64SSCOFPMF %s
@@ -396,6 +398,7 @@
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; RV32SHCOUNTERENW: .attribute 5, "rv32i2p1_shcounterenw1p0"
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; RV32SHGATPA: .attribute 5, "rv32i2p1_shgatpa1p0"
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; RV32SHVSATPA: .attribute 5, "rv32i2p1_shvsatpa1p0"
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; RV32SHLCOFIDELEG: .attribute 5, "rv32i2p1_shlcofideleg1p0"
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; RV32SSCCFG: .attribute 5, "rv32i2p1_ssccfg1p0"
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; RV32SSCCPTR: .attribute 5, "rv32i2p1_ssccptr1p0"
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; RV32SSCOFPMF: .attribute 5, "rv32i2p1_sscofpmf1p0"
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; RV64SHCOUNTERENW: .attribute 5, "rv64i2p1_shcounterenw1p0"
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; RV64SHGATPA: .attribute 5, "rv64i2p1_shgatpa1p0"
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; RV64SHVSATPA: .attribute 5, "rv64i2p1_shvsatpa1p0"
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; RV64SHLCOFIDELEG: .attribute 5, "rv64i2p1_shlcofideleg1p0"
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; RV64SSCCFG: .attribute 5, "rv64i2p1_ssccfg1p0"
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; RV64SSCCPTR: .attribute 5, "rv64i2p1_ssccptr1p0"
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; RV64SSCOFPMF: .attribute 5, "rv64i2p1_sscofpmf1p0"

‎llvm/test/CodeGen/RISCV/features-info.ll

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; CHECK-NEXT: shcounterenw - 'Shcounterenw' (Support writeable hcounteren enable bit for any hpmcounter that is not read-only zero).
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; CHECK-NEXT: shgatpa - 'Shgatpa' (SvNNx4 mode supported for all modes supported by satp, as well as Bare).
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; CHECK-NEXT: shifted-zextw-fusion - Enable SLLI+SRLI to be fused when computing (shifted) word zero extension.
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; CHECK-NEXT: shlcofideleg - 'Shlcofideleg' (Delegating LCOFI Interrupts to VS-mode).
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; CHECK-NEXT: short-forward-branch-opt - Enable short forward branch optimization.
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; CHECK-NEXT: shtvala - 'Shtvala' (htval provides all needed values).
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; CHECK-NEXT: shvsatpa - 'Shvsatpa' (vsatp supports all modes supported by satp).

‎llvm/test/MC/RISCV/attribute-arch.s

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.attribute arch, "rv32i_shvsatpa1p0"
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# CHECK: attribute 5, "rv32i2p1_shvsatpa1p0"
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.attribute arch, "rv32i_shlcofideleg1p0"
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# CHECK: attribute 5, "rv32i2p1_shlcofideleg1p0"
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.attribute arch, "rv32i_shtvala1p0"
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# CHECK: attribute 5, "rv32i2p1_shtvala1p0"
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‎llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

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sha 1.0
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shcounterenw 1.0
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shgatpa 1.0
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shlcofideleg 1.0
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shtvala 1.0
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shvsatpa 1.0
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shvstvala 1.0

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