[RISCV][GISel] Fix test case order in fp-arith.mir. NFC

The fadd_f64 test was in the middle of some f32 tests.

Author: topperc

llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith.mir

@@ -191,30 +191,6 @@ body:             |
     $f10_f = COPY %1(s32)
     PseudoRET implicit $f10_f
 
-...
----
-name:            fadd_f64
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-body:             |
-  bb.0:
-    liveins: $f10_d, $f11_d
-
-    ; CHECK-LABEL: name: fadd_f64
-    ; CHECK: liveins: $f10_d, $f11_d
-    ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
-    ; CHECK-NEXT: [[FADD_D:%[0-9]+]]:fpr64 = nofpexcept FADD_D [[COPY]], [[COPY1]], 7
-    ; CHECK-NEXT: $f10_d = COPY [[FADD_D]]
-    ; CHECK-NEXT: PseudoRET implicit $f10_d
-    %0:fprb(s64) = COPY $f10_d
-    %1:fprb(s64) = COPY $f11_d
-    %2:fprb(s64) = G_FADD %0, %1
-    $f10_d = COPY %2(s64)
-    PseudoRET implicit $f10_d
-
 ...
 ---
 name:            fmaxnum_f32
@@ -287,6 +263,30 @@ body:             |
     $f10_f = COPY %2(s32)
     PseudoRET implicit $f10_f
 
+...
+---
+name:            fadd_f64
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $f10_d, $f11_d
+
+    ; CHECK-LABEL: name: fadd_f64
+    ; CHECK: liveins: $f10_d, $f11_d
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
+    ; CHECK-NEXT: [[FADD_D:%[0-9]+]]:fpr64 = nofpexcept FADD_D [[COPY]], [[COPY1]], 7
+    ; CHECK-NEXT: $f10_d = COPY [[FADD_D]]
+    ; CHECK-NEXT: PseudoRET implicit $f10_d
+    %0:fprb(s64) = COPY $f10_d
+    %1:fprb(s64) = COPY $f11_d
+    %2:fprb(s64) = G_FADD %0, %1
+    $f10_d = COPY %2(s64)
+    PseudoRET implicit $f10_d
+
 ...
 ---
 name:            fsub_f64