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[X86] Use Register and MCRegister. NFC
1 parent 0689d23 commit 3fe914c

21 files changed

+105
-108
lines changed

‎llvm/lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -533,7 +533,7 @@ void X86AvoidSFBPass::findPotentiallylBlockedCopies(MachineFunction &MF) {
533533
for (auto &MI : MBB) {
534534
if (!isPotentialBlockedMemCpyLd(MI.getOpcode()))
535535
continue;
536-
int DefVR = MI.getOperand(0).getReg();
536+
Register DefVR = MI.getOperand(0).getReg();
537537
if (!MRI->hasOneNonDBGUse(DefVR))
538538
continue;
539539
for (MachineOperand &StoreMO :

‎llvm/lib/Target/X86/X86CallFrameOptimization.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -112,7 +112,7 @@ class X86CallFrameOptimization : public MachineFunctionPass {
112112
InstClassification classifyInstruction(MachineBasicBlock &MBB,
113113
MachineBasicBlock::iterator MI,
114114
const X86RegisterInfo &RegInfo,
115-
DenseSet<unsigned int> &UsedRegs);
115+
const DenseSet<MCRegister> &UsedRegs);
116116

117117
StringRef getPassName() const override { return "X86 Optimize Call Frame"; }
118118

@@ -278,7 +278,7 @@ bool X86CallFrameOptimization::runOnMachineFunction(MachineFunction &MF) {
278278
X86CallFrameOptimization::InstClassification
279279
X86CallFrameOptimization::classifyInstruction(
280280
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
281-
const X86RegisterInfo &RegInfo, DenseSet<unsigned int> &UsedRegs) {
281+
const X86RegisterInfo &RegInfo, const DenseSet<MCRegister> &UsedRegs) {
282282
if (MI == MBB.end())
283283
return Exit;
284284

@@ -341,7 +341,7 @@ X86CallFrameOptimization::classifyInstruction(
341341
if (RegInfo.regsOverlap(Reg, RegInfo.getStackRegister()))
342342
return Exit;
343343
if (MO.isDef()) {
344-
for (unsigned int U : UsedRegs)
344+
for (MCRegister U : UsedRegs)
345345
if (RegInfo.regsOverlap(Reg, U))
346346
return Exit;
347347
}
@@ -406,7 +406,7 @@ void X86CallFrameOptimization::collectCallInfo(MachineFunction &MF,
406406
if (MaxAdjust > 4)
407407
Context.ArgStoreVector.resize(MaxAdjust, nullptr);
408408

409-
DenseSet<unsigned int> UsedRegs;
409+
DenseSet<MCRegister> UsedRegs;
410410

411411
for (InstClassification Classification = Skip; Classification != Exit; ++I) {
412412
// If this is the COPY of the stack pointer, it's ok to ignore.
@@ -455,7 +455,7 @@ void X86CallFrameOptimization::collectCallInfo(MachineFunction &MF,
455455
continue;
456456
Register Reg = MO.getReg();
457457
if (Reg.isPhysical())
458-
UsedRegs.insert(Reg);
458+
UsedRegs.insert(Reg.asMCReg());
459459
}
460460
}
461461

‎llvm/lib/Target/X86/X86CmovConversion.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -406,7 +406,7 @@ bool X86CmovConverterPass::checkForProfitableCmovCandidates(
406406
DepthInfo LoopDepth[LoopIterations] = {{0, 0}, {0, 0}};
407407
enum { PhyRegType = 0, VirRegType = 1, RegTypeNum = 2 };
408408
/// For each register type maps the register to its last def instruction.
409-
DenseMap<unsigned, MachineInstr *> RegDefMaps[RegTypeNum];
409+
DenseMap<Register, MachineInstr *> RegDefMaps[RegTypeNum];
410410
/// Maps register operand to its def instruction, which can be nullptr if it
411411
/// is unknown (e.g., operand is defined outside the loop).
412412
DenseMap<MachineOperand *, MachineInstr *> OperandToDefMap;
@@ -723,7 +723,7 @@ void X86CmovConverterPass::convertCmovInstsToBranches(
723723
// operand. We also need to potentially do register rewriting here, but it is
724724
// simpler as the memory operands are always on the false path so we can
725725
// simply take that input, whatever it is.
726-
DenseMap<unsigned, unsigned> FalseBBRegRewriteTable;
726+
DenseMap<Register, Register> FalseBBRegRewriteTable;
727727
for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd;) {
728728
auto &MI = *MIIt++;
729729
// Skip any CMOVs in this group which don't load from memory.
@@ -830,7 +830,7 @@ void X86CmovConverterPass::convertCmovInstsToBranches(
830830
// That also means that PHI construction must work forward from earlier to
831831
// later, and that the code must maintain a mapping from earlier PHI's
832832
// destination registers, and the registers that went into the PHI.
833-
DenseMap<unsigned, std::pair<unsigned, unsigned>> RegRewriteTable;
833+
DenseMap<Register, std::pair<Register, Register>> RegRewriteTable;
834834

835835
for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; ++MIIt) {
836836
Register DestReg = MIIt->getOperand(0).getReg();

‎llvm/lib/Target/X86/X86CompressEVEX.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -83,7 +83,7 @@ class CompressEVEXPass : public MachineFunctionPass {
8383
char CompressEVEXPass::ID = 0;
8484

8585
static bool usesExtendedRegister(const MachineInstr &MI) {
86-
auto isHiRegIdx = [](unsigned Reg) {
86+
auto isHiRegIdx = [](MCRegister Reg) {
8787
// Check for XMM register with indexes between 16 - 31.
8888
if (Reg >= X86::XMM16 && Reg <= X86::XMM31)
8989
return true;
@@ -102,7 +102,7 @@ static bool usesExtendedRegister(const MachineInstr &MI) {
102102
if (!MO.isReg())
103103
continue;
104104

105-
Register Reg = MO.getReg();
105+
MCRegister Reg = MO.getReg().asMCReg();
106106
assert(!X86II::isZMMReg(Reg) &&
107107
"ZMM instructions should not be in the EVEX->VEX tables");
108108
if (isHiRegIdx(Reg))

‎llvm/lib/Target/X86/X86DomainReassignment.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -400,7 +400,7 @@ class X86DomainReassignment : public MachineFunctionPass {
400400
/// Enqueue \p Reg to be considered for addition to the closure.
401401
/// Return false if the closure becomes invalid.
402402
bool visitRegister(Closure &, Register Reg, RegDomain &Domain,
403-
SmallVectorImpl<unsigned> &Worklist);
403+
SmallVectorImpl<Register> &Worklist);
404404

405405
/// Reassign the closure to \p Domain.
406406
void reassign(const Closure &C, RegDomain Domain) const;
@@ -422,7 +422,7 @@ char X86DomainReassignment::ID = 0;
422422

423423
bool X86DomainReassignment::visitRegister(Closure &C, Register Reg,
424424
RegDomain &Domain,
425-
SmallVectorImpl<unsigned> &Worklist) {
425+
SmallVectorImpl<Register> &Worklist) {
426426
if (!Reg.isVirtual())
427427
return true;
428428

@@ -544,11 +544,11 @@ static bool usedAsAddr(const MachineInstr &MI, Register Reg,
544544
}
545545

546546
void X86DomainReassignment::buildClosure(Closure &C, Register Reg) {
547-
SmallVector<unsigned, 4> Worklist;
547+
SmallVector<Register, 4> Worklist;
548548
RegDomain Domain = NoDomain;
549549
visitRegister(C, Reg, Domain, Worklist);
550550
while (!Worklist.empty()) {
551-
unsigned CurReg = Worklist.pop_back_val();
551+
Register CurReg = Worklist.pop_back_val();
552552

553553
// Register already in this closure.
554554
if (!C.insertEdge(CurReg))

‎llvm/lib/Target/X86/X86DynAllocaExpander.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -57,7 +57,7 @@ class X86DynAllocaExpander : public MachineFunctionPass {
5757
const X86Subtarget *STI = nullptr;
5858
const TargetInstrInfo *TII = nullptr;
5959
const X86RegisterInfo *TRI = nullptr;
60-
unsigned StackPtr = 0;
60+
Register StackPtr;
6161
unsigned SlotSize = 0;
6262
int64_t StackProbeSize = 0;
6363
bool NoStackArgProbe = false;

‎llvm/lib/Target/X86/X86FastISel.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2684,7 +2684,7 @@ bool X86FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
26842684
MFI.setFrameAddressIsTaken(true);
26852685

26862686
const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
2687-
unsigned FrameReg = RegInfo->getPtrSizedFrameRegister(*MF);
2687+
Register FrameReg = RegInfo->getPtrSizedFrameRegister(*MF);
26882688
assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
26892689
(FrameReg == X86::EBP && VT == MVT::i32)) &&
26902690
"Invalid Frame Register!");
@@ -3478,7 +3478,7 @@ bool X86FastISel::fastLowerCall(CallLoweringInfo &CLI) {
34783478
// ELF / PIC requires GOT in the EBX register before function calls via PLT
34793479
// GOT pointer.
34803480
if (Subtarget->isPICStyleGOT()) {
3481-
unsigned Base = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
3481+
Register Base = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
34823482
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
34833483
TII.get(TargetOpcode::COPY), X86::EBX).addReg(Base);
34843484
}
@@ -3510,11 +3510,11 @@ bool X86FastISel::fastLowerCall(CallLoweringInfo &CLI) {
35103510
if (!X86SelectCallAddress(Callee, CalleeAM))
35113511
return false;
35123512

3513-
unsigned CalleeOp = 0;
3513+
Register CalleeOp;
35143514
const GlobalValue *GV = nullptr;
35153515
if (CalleeAM.GV != nullptr) {
35163516
GV = CalleeAM.GV;
3517-
} else if (CalleeAM.Base.Reg != 0) {
3517+
} else if (CalleeAM.Base.Reg) {
35183518
CalleeOp = CalleeAM.Base.Reg;
35193519
} else
35203520
return false;
@@ -3816,7 +3816,7 @@ Register X86FastISel::X86MaterializeFP(const ConstantFP *CFP, MVT VT) {
38163816
Align Alignment = DL.getPrefTypeAlign(CFP->getType());
38173817

38183818
// x86-32 PIC requires a PIC base register for constant pools.
3819-
unsigned PICBase = 0;
3819+
Register PICBase;
38203820
unsigned char OpFlag = Subtarget->classifyLocalReference(nullptr);
38213821
if (OpFlag == X86II::MO_PIC_BASE_OFFSET)
38223822
PICBase = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);

‎llvm/lib/Target/X86/X86FixupLEAs.cpp

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -325,7 +325,7 @@ FixupLEAPass::searchBackwards(MachineOperand &p, MachineBasicBlock::iterator &I,
325325
return MachineBasicBlock::iterator();
326326
}
327327

328-
static inline bool isInefficientLEAReg(unsigned Reg) {
328+
static inline bool isInefficientLEAReg(Register Reg) {
329329
return Reg == X86::EBP || Reg == X86::RBP ||
330330
Reg == X86::R13D || Reg == X86::R13;
331331
}
@@ -337,7 +337,7 @@ static inline bool isInefficientLEAReg(unsigned Reg) {
337337
static inline bool hasInefficientLEABaseReg(const MachineOperand &Base,
338338
const MachineOperand &Index) {
339339
return Base.isReg() && isInefficientLEAReg(Base.getReg()) && Index.isReg() &&
340-
Index.getReg() != X86::NoRegister;
340+
Index.getReg().isValid();
341341
}
342342

343343
static inline bool hasLEAOffset(const MachineOperand &Offset) {
@@ -557,7 +557,7 @@ bool FixupLEAPass::optTwoAddrLEA(MachineBasicBlock::iterator &I,
557557
const MachineOperand &Disp = MI.getOperand(1 + X86::AddrDisp);
558558
const MachineOperand &Segment = MI.getOperand(1 + X86::AddrSegmentReg);
559559

560-
if (Segment.getReg() != 0 || !Disp.isImm() || Scale.getImm() > 1 ||
560+
if (Segment.getReg().isValid() || !Disp.isImm() || Scale.getImm() > 1 ||
561561
MBB.computeRegisterLiveness(TRI, X86::EFLAGS, I) !=
562562
MachineBasicBlock::LQR_Dead)
563563
return false;
@@ -572,9 +572,9 @@ bool FixupLEAPass::optTwoAddrLEA(MachineBasicBlock::iterator &I,
572572

573573
// LEA64_32 has 64-bit operands but 32-bit result.
574574
if (MI.getOpcode() == X86::LEA64_32r) {
575-
if (BaseReg != 0)
575+
if (BaseReg)
576576
BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit);
577-
if (IndexReg != 0)
577+
if (IndexReg)
578578
IndexReg = TRI->getSubReg(IndexReg, X86::sub_32bit);
579579
}
580580

@@ -583,7 +583,7 @@ bool FixupLEAPass::optTwoAddrLEA(MachineBasicBlock::iterator &I,
583583
// Case 1.
584584
// Look for lea(%reg1, %reg2), %reg1 or lea(%reg2, %reg1), %reg1
585585
// which can be turned into add %reg2, %reg1
586-
if (BaseReg != 0 && IndexReg != 0 && Disp.getImm() == 0 &&
586+
if (BaseReg.isValid() && IndexReg.isValid() && Disp.getImm() == 0 &&
587587
(DestReg == BaseReg || DestReg == IndexReg)) {
588588
unsigned NewOpcode = getADDrrFromLEA(MI.getOpcode());
589589
if (DestReg != BaseReg)
@@ -599,7 +599,7 @@ bool FixupLEAPass::optTwoAddrLEA(MachineBasicBlock::iterator &I,
599599
NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
600600
.addReg(BaseReg).addReg(IndexReg);
601601
}
602-
} else if (DestReg == BaseReg && IndexReg == 0) {
602+
} else if (DestReg == BaseReg && !IndexReg) {
603603
// Case 2.
604604
// This is an LEA with only a base register and a displacement,
605605
// We can use ADDri or INC/DEC.
@@ -631,7 +631,7 @@ bool FixupLEAPass::optTwoAddrLEA(MachineBasicBlock::iterator &I,
631631
.addReg(BaseReg).addImm(Disp.getImm());
632632
}
633633
}
634-
} else if (BaseReg != 0 && IndexReg != 0 && Disp.getImm() == 0) {
634+
} else if (BaseReg.isValid() && IndexReg.isValid() && Disp.getImm() == 0) {
635635
// Case 3.
636636
// Look for and transform the sequence
637637
// lea (reg1, reg2), reg3
@@ -697,22 +697,22 @@ void FixupLEAPass::processInstructionForSlowLEA(MachineBasicBlock::iterator &I,
697697
const MachineOperand &Offset = MI.getOperand(1 + X86::AddrDisp);
698698
const MachineOperand &Segment = MI.getOperand(1 + X86::AddrSegmentReg);
699699

700-
if (Segment.getReg() != 0 || !Offset.isImm() ||
700+
if (Segment.getReg().isValid() || !Offset.isImm() ||
701701
MBB.computeRegisterLiveness(TRI, X86::EFLAGS, I, 4) !=
702702
MachineBasicBlock::LQR_Dead)
703703
return;
704704
const Register DstR = Dst.getReg();
705705
const Register SrcR1 = Base.getReg();
706706
const Register SrcR2 = Index.getReg();
707-
if ((SrcR1 == 0 || SrcR1 != DstR) && (SrcR2 == 0 || SrcR2 != DstR))
707+
if ((!SrcR1 || SrcR1 != DstR) && (!SrcR2 || SrcR2 != DstR))
708708
return;
709709
if (Scale.getImm() > 1)
710710
return;
711711
LLVM_DEBUG(dbgs() << "FixLEA: Candidate to replace:"; I->dump(););
712712
LLVM_DEBUG(dbgs() << "FixLEA: Replaced by: ";);
713713
MachineInstr *NewMI = nullptr;
714714
// Make ADD instruction for two registers writing to LEA's destination
715-
if (SrcR1 != 0 && SrcR2 != 0) {
715+
if (SrcR1 && SrcR2) {
716716
const MCInstrDesc &ADDrr = TII->get(getADDrrFromLEA(Opcode));
717717
const MachineOperand &Src = SrcR1 == DstR ? Index : Base;
718718
NewMI =
@@ -752,17 +752,17 @@ void FixupLEAPass::processInstrForSlow3OpLEA(MachineBasicBlock::iterator &I,
752752
if (!(TII->isThreeOperandsLEA(MI) || hasInefficientLEABaseReg(Base, Index)) ||
753753
MBB.computeRegisterLiveness(TRI, X86::EFLAGS, I, 4) !=
754754
MachineBasicBlock::LQR_Dead ||
755-
Segment.getReg() != X86::NoRegister)
755+
Segment.getReg().isValid())
756756
return;
757757

758758
Register DestReg = Dest.getReg();
759759
Register BaseReg = Base.getReg();
760760
Register IndexReg = Index.getReg();
761761

762762
if (MI.getOpcode() == X86::LEA64_32r) {
763-
if (BaseReg != 0)
763+
if (BaseReg)
764764
BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit);
765-
if (IndexReg != 0)
765+
if (IndexReg)
766766
IndexReg = TRI->getSubReg(IndexReg, X86::sub_32bit);
767767
}
768768

‎llvm/lib/Target/X86/X86FlagsCopyLowering.cpp

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -69,7 +69,7 @@ STATISTIC(NumNFsConvertedTo, "Number of NF instructions converted to");
6969
namespace {
7070

7171
// Convenient array type for storing registers associated with each condition.
72-
using CondRegArray = std::array<unsigned, X86::LAST_VALID_COND + 1>;
72+
using CondRegArray = std::array<Register, X86::LAST_VALID_COND + 1>;
7373

7474
class X86FlagsCopyLoweringPass : public MachineFunctionPass {
7575
public:
@@ -96,11 +96,11 @@ class X86FlagsCopyLoweringPass : public MachineFunctionPass {
9696
Register promoteCondToReg(MachineBasicBlock &MBB,
9797
MachineBasicBlock::iterator TestPos,
9898
const DebugLoc &TestLoc, X86::CondCode Cond);
99-
std::pair<unsigned, bool> getCondOrInverseInReg(
99+
std::pair<Register, bool> getCondOrInverseInReg(
100100
MachineBasicBlock &TestMBB, MachineBasicBlock::iterator TestPos,
101101
const DebugLoc &TestLoc, X86::CondCode Cond, CondRegArray &CondRegs);
102102
void insertTest(MachineBasicBlock &MBB, MachineBasicBlock::iterator Pos,
103-
const DebugLoc &Loc, unsigned Reg);
103+
const DebugLoc &Loc, Register Reg);
104104

105105
void rewriteSetCC(MachineBasicBlock &MBB, MachineBasicBlock::iterator Pos,
106106
const DebugLoc &Loc, MachineInstr &MI,
@@ -744,11 +744,11 @@ Register X86FlagsCopyLoweringPass::promoteCondToReg(
744744
return Reg;
745745
}
746746

747-
std::pair<unsigned, bool> X86FlagsCopyLoweringPass::getCondOrInverseInReg(
747+
std::pair<Register, bool> X86FlagsCopyLoweringPass::getCondOrInverseInReg(
748748
MachineBasicBlock &TestMBB, MachineBasicBlock::iterator TestPos,
749749
const DebugLoc &TestLoc, X86::CondCode Cond, CondRegArray &CondRegs) {
750-
unsigned &CondReg = CondRegs[Cond];
751-
unsigned &InvCondReg = CondRegs[X86::GetOppositeBranchCondition(Cond)];
750+
Register &CondReg = CondRegs[Cond];
751+
Register &InvCondReg = CondRegs[X86::GetOppositeBranchCondition(Cond)];
752752
if (!CondReg && !InvCondReg)
753753
CondReg = promoteCondToReg(TestMBB, TestPos, TestLoc, Cond);
754754

@@ -760,7 +760,7 @@ std::pair<unsigned, bool> X86FlagsCopyLoweringPass::getCondOrInverseInReg(
760760

761761
void X86FlagsCopyLoweringPass::insertTest(MachineBasicBlock &MBB,
762762
MachineBasicBlock::iterator Pos,
763-
const DebugLoc &Loc, unsigned Reg) {
763+
const DebugLoc &Loc, Register Reg) {
764764
auto TestI =
765765
BuildMI(MBB, Pos, Loc, TII->get(X86::TEST8rr)).addReg(Reg).addReg(Reg);
766766
(void)TestI;
@@ -777,7 +777,7 @@ void X86FlagsCopyLoweringPass::rewriteSetCC(MachineBasicBlock &MBB,
777777
// Note that we can't usefully rewrite this to the inverse without complex
778778
// analysis of the users of the setCC. Largely we rely on duplicates which
779779
// could have been avoided already being avoided here.
780-
unsigned &CondReg = CondRegs[Cond];
780+
Register &CondReg = CondRegs[Cond];
781781
if (!CondReg)
782782
CondReg = promoteCondToReg(MBB, Pos, Loc, Cond);
783783

@@ -843,7 +843,7 @@ void X86FlagsCopyLoweringPass::rewriteArithmetic(
843843
// Now get a register that contains the value of the flag input to the
844844
// arithmetic. We require exactly this flag to simplify the arithmetic
845845
// required to materialize it back into the flag.
846-
unsigned &CondReg = CondRegs[Cond];
846+
Register &CondReg = CondRegs[Cond];
847847
if (!CondReg)
848848
CondReg = promoteCondToReg(MBB, Pos, Loc, Cond);
849849

@@ -917,7 +917,7 @@ void X86FlagsCopyLoweringPass::rewriteMI(MachineBasicBlock &MBB,
917917
IsImplicitCC = true;
918918
}
919919
assert(CC != X86::COND_INVALID && "Unknown EFLAG user!");
920-
unsigned CondReg;
920+
Register CondReg;
921921
bool Inverted;
922922
std::tie(CondReg, Inverted) =
923923
getCondOrInverseInReg(MBB, Pos, Loc, CC, CondRegs);

‎llvm/lib/Target/X86/X86FloatingPoint.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -462,7 +462,7 @@ bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
462462

463463
// Get dead variables list now because the MI pointer may be deleted as part
464464
// of processing!
465-
SmallVector<unsigned, 8> DeadRegs;
465+
SmallVector<Register, 8> DeadRegs;
466466
for (const MachineOperand &MO : MI.operands())
467467
if (MO.isReg() && MO.isDead())
468468
DeadRegs.push_back(MO.getReg());
@@ -480,7 +480,7 @@ bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
480480

481481
// Check to see if any of the values defined by this instruction are dead
482482
// after definition. If so, pop them.
483-
for (unsigned Reg : DeadRegs) {
483+
for (Register Reg : DeadRegs) {
484484
// Check if Reg is live on the stack. An inline-asm register operand that
485485
// is in the clobber list and marked dead might not be live on the stack.
486486
static_assert(X86::FP7 - X86::FP0 == 7, "sequential FP regnumbers");

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