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[ARM]: codegen llvm.roundeven.v* 
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6 files changed

+115
-3
lines changed

6 files changed

+115
-3
lines changed

‎llvm/lib/Target/ARM/ARMISelLowering.cpp

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -905,6 +905,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
905905
setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
906906
setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
907907
setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
908+
setOperationAction(ISD::FROUNDEVEN, MVT::v2f64, Expand);
908909
setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
909910
setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
910911
setOperationAction(ISD::FMA, MVT::v2f64, Expand);
@@ -927,6 +928,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
927928
setOperationAction(ISD::FCEIL, MVT::v4f32, Expand);
928929
setOperationAction(ISD::FTRUNC, MVT::v4f32, Expand);
929930
setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
931+
setOperationAction(ISD::FROUNDEVEN, MVT::v4f32, Expand);
930932
setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
931933
setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand);
932934

@@ -945,6 +947,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
945947
setOperationAction(ISD::FCEIL, MVT::v2f32, Expand);
946948
setOperationAction(ISD::FTRUNC, MVT::v2f32, Expand);
947949
setOperationAction(ISD::FRINT, MVT::v2f32, Expand);
950+
setOperationAction(ISD::FROUNDEVEN, MVT::v2f32, Expand);
948951
setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand);
949952
setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand);
950953

@@ -1087,6 +1090,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
10871090
setOperationAction(ISD::FCEIL, MVT::f64, Expand);
10881091
setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
10891092
setOperationAction(ISD::FRINT, MVT::f64, Expand);
1093+
setOperationAction(ISD::FROUNDEVEN, MVT::f64, Expand);
10901094
setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
10911095
setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
10921096
setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
@@ -1534,6 +1538,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
15341538
setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
15351539
setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
15361540
setOperationAction(ISD::FRINT, MVT::f32, Legal);
1541+
setOperationAction(ISD::FROUNDEVEN, MVT::f32, Legal);
15371542
setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
15381543
setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
15391544
if (Subtarget->hasNEON()) {
@@ -1550,6 +1555,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
15501555
setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
15511556
setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
15521557
setOperationAction(ISD::FRINT, MVT::f64, Legal);
1558+
setOperationAction(ISD::FROUNDEVEN, MVT::f64, Legal);
15531559
setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
15541560
setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
15551561
}

‎llvm/lib/Target/ARM/ARMInstrNEON.td

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7312,8 +7312,13 @@ multiclass VRINT_FPI<string op, bits<3> op9_7, SDPatternOperator Int> {
73127312
}
73137313
}
73147314

7315+
def vfrint_or_froundeven : PatFrags<(ops node:$src), [
7316+
(int_arm_neon_vrintx node:$src),
7317+
(any_froundeven node:$src)
7318+
]>;
7319+
73157320
defm VRINTNN : VRINT_FPI<"n", 0b000, int_arm_neon_vrintn>;
7316-
defm VRINTXN : VRINT_FPI<"x", 0b001, int_arm_neon_vrintx>;
7321+
defm VRINTXN : VRINT_FPI<"x", 0b001, vfrint_or_froundeven>;
73177322
defm VRINTAN : VRINT_FPI<"a", 0b010, int_arm_neon_vrinta>;
73187323
defm VRINTZN : VRINT_FPI<"z", 0b011, int_arm_neon_vrintz>;
73197324
defm VRINTMN : VRINT_FPI<"m", 0b101, int_arm_neon_vrintm>;

‎llvm/lib/Target/ARM/ARMInstrVFP.td

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1093,9 +1093,14 @@ multiclass vrint_inst_zrx<string opc, bit op, bit op2, SDPatternOperator node> {
10931093
Requires<[HasFPARMv8,HasDPVFP]>;
10941094
}
10951095

1096+
def frint_or_froundeven : PatFrags<(ops node:$src), [
1097+
(frint node:$src),
1098+
(any_froundeven node:$src)
1099+
]>;
1100+
10961101
defm VRINTZ : vrint_inst_zrx<"z", 0, 1, ftrunc>;
10971102
defm VRINTR : vrint_inst_zrx<"r", 0, 0, fnearbyint>;
1098-
defm VRINTX : vrint_inst_zrx<"x", 1, 0, frint>;
1103+
defm VRINTX : vrint_inst_zrx<"x", 1, 0, frint_or_froundeven>;
10991104

11001105
multiclass vrint_inst_anpm<string opc, bits<2> rm,
11011106
SDPatternOperator node = null_frag> {

‎llvm/test/CodeGen/ARM/arm32-rounding.ll

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -104,6 +104,22 @@ entry:
104104
ret double %call
105105
}
106106

107+
; CHECK-LABEL: test13
108+
; CHECK: vrintx.f32
109+
define float @test13(float %a) {
110+
entry:
111+
%round = call float @llvm.roundeven.f32(float %a)
112+
ret float %round
113+
}
114+
115+
; CHECK-LABEL: test14
116+
; CHECK: vrintx.f64
117+
define double @test14(double %a) {
118+
entry:
119+
%round = call double @llvm.roundeven.f64(double %a)
120+
ret double %round
121+
}
122+
107123
declare float @floorf(float) nounwind readnone
108124
declare double @floor(double) nounwind readnone
109125
declare float @ceilf(float) nounwind readnone
@@ -116,3 +132,5 @@ declare float @nearbyintf(float) nounwind readnone
116132
declare double @nearbyint(double) nounwind readnone
117133
declare float @rintf(float) nounwind readnone
118134
declare double @rint(double) nounwind readnone
135+
declare float @llvm.roundeven.f32(float)
136+
declare double @llvm.roundeven.f64(double)

‎llvm/test/CodeGen/ARM/frintn.ll

Lines changed: 78 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,78 @@
1+
; RUN: llc -mtriple=armv8 -mattr=+neon %s -o - | FileCheck %s
2+
3+
; The llvm.arm.neon.frintn intrinsic should be auto-upgraded to the
4+
; target-independent roundeven intrinsic.
5+
6+
define <4 x half> @frintn_4h(<4 x half> %A) nounwind {
7+
;CHECK-LABEL: frintn_4h:
8+
;CHECK: bl llvm.arm.neon.frintn.v4f16
9+
%tmp3 = call <4 x half> @llvm.arm.neon.frintn.v4f16(<4 x half> %A)
10+
ret <4 x half> %tmp3
11+
}
12+
13+
define <2 x float> @frintn_2s(<2 x float> %A) nounwind {
14+
;CHECK-LABEL: frintn_2s:
15+
;CHECK: bl llvm.arm.neon.frintn.v2f32
16+
%tmp3 = call <2 x float> @llvm.arm.neon.frintn.v2f32(<2 x float> %A)
17+
ret <2 x float> %tmp3
18+
}
19+
20+
define <4 x float> @frintn_4s(<4 x float> %A) nounwind {
21+
;CHECK-LABEL: frintn_4s:
22+
;CHECK: bl llvm.arm.neon.frintn.v4f32
23+
%tmp3 = call <4 x float> @llvm.arm.neon.frintn.v4f32(<4 x float> %A)
24+
ret <4 x float> %tmp3
25+
}
26+
27+
define <2 x double> @frintn_2d(<2 x double> %A) nounwind {
28+
;CHECK-LABEL: frintn_2d:
29+
;CHECK: bl llvm.arm.neon.frintn.v2f64
30+
%tmp3 = call <2 x double> @llvm.arm.neon.frintn.v2f64(<2 x double> %A)
31+
ret <2 x double> %tmp3
32+
}
33+
34+
declare <4 x half> @llvm.arm.neon.frintn.v4f16(<4 x half>) nounwind readnone
35+
declare <2 x float> @llvm.arm.neon.frintn.v2f32(<2 x float>) nounwind readnone
36+
declare <4 x float> @llvm.arm.neon.frintn.v4f32(<4 x float>) nounwind readnone
37+
declare <2 x double> @llvm.arm.neon.frintn.v2f64(<2 x double>) nounwind readnone
38+
39+
define <4 x half> @roundeven_4h(<4 x half> %A) nounwind {
40+
;CHECK-LABEL: roundeven_4h:
41+
;CHECK: vcvtb.f16.f32 s0, s0
42+
;CHECK: vrintx.f32 s2, s2
43+
;CHECK: vmov r0, s0
44+
;CHECK: vcvtb.f16.f32 s2, s2
45+
%tmp3 = call <4 x half> @llvm.roundeven.v4f16(<4 x half> %A)
46+
ret <4 x half> %tmp3
47+
}
48+
49+
define <2 x float> @roundeven_2s(<2 x float> %A) nounwind {
50+
;CHECK-LABEL: roundeven_2s:
51+
;CHECK: vrintx.f32 s3, s1
52+
;CHECK: vrintx.f32 s2, s0
53+
%tmp3 = call <2 x float> @llvm.roundeven.v2f32(<2 x float> %A)
54+
ret <2 x float> %tmp3
55+
}
56+
57+
define <4 x float> @roundeven_4s(<4 x float> %A) nounwind {
58+
;CHECK-LABEL: roundeven_4s:
59+
;CHECK: vrintx.f32 s7, s3
60+
;CHECK: vrintx.f32 s6, s2
61+
;CHECK: vrintx.f32 s5, s1
62+
;CHECK: vrintx.f32 s4, s0
63+
%tmp3 = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %A)
64+
ret <4 x float> %tmp3
65+
}
66+
67+
define <2 x double> @roundeven_2d(<2 x double> %A) nounwind {
68+
;CHECK-LABEL: roundeven_2d:
69+
;CHECK: vrintx.f64 d16, d16
70+
;CHECK: vrintx.f64 d17, d17
71+
%tmp3 = call <2 x double> @llvm.roundeven.v2f64(<2 x double> %A)
72+
ret <2 x double> %tmp3
73+
}
74+
75+
declare <4 x half> @llvm.roundeven.v4f16(<4 x half>) nounwind readnone
76+
declare <2 x float> @llvm.roundeven.v2f32(<2 x float>) nounwind readnone
77+
declare <4 x float> @llvm.roundeven.v4f32(<4 x float>) nounwind readnone
78+
declare <2 x double> @llvm.roundeven.v2f64(<2 x double>) nounwind readnone

‎llvm/test/CodeGen/Thumb2/bf16-instructions.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2373,7 +2373,7 @@ define bfloat @test_roundeven(bfloat %a) {
23732373
; CHECK-FP-NEXT: vmov r0, s0
23742374
; CHECK-FP-NEXT: lsls r0, r0, #16
23752375
; CHECK-FP-NEXT: vmov s0, r0
2376-
; CHECK-FP-NEXT: bl roundevenf
2376+
; CHECK-FP-NEXT: vrintx.f32 s0, s0
23772377
; CHECK-FP-NEXT: bl __truncsfbf2
23782378
; CHECK-FP-NEXT: vmov.f16 r0, s0
23792379
; CHECK-FP-NEXT: vmov s0, r0

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