Fix PromoteHalf support

Author: wzssyqa

llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

@@ -2639,7 +2639,11 @@ SDValue DAGTypeLegalizer::PromoteFloatOp_FCOPYSIGN(SDNode *N, unsigned OpNo) {
 // Convert the promoted float value to the desired integer type
 SDValue DAGTypeLegalizer::PromoteFloatOp_UnaryOp(SDNode *N, unsigned OpNo) {
   SDValue Op = GetPromotedFloat(N->getOperand(0));
-  return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0), Op);
+  if (N->getOpcode() == ISD::AssertNoFPClass)
+    return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0), Op,
+                       N->getOperand(1));
+  else
+    return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0), Op);
 }
 
 SDValue DAGTypeLegalizer::PromoteFloatOp_FP_TO_XINT_SAT(SDNode *N,
@@ -2999,8 +3003,10 @@ SDValue DAGTypeLegalizer::PromoteFloatRes_UnaryOp(SDNode *N) {
   EVT VT = N->getValueType(0);
   EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
   SDValue Op = GetPromotedFloat(N->getOperand(0));
-
-  return DAG.getNode(N->getOpcode(), SDLoc(N), NVT, Op);
+  if (N->getOpcode() == ISD::AssertNoFPClass)
+    return DAG.getNode(N->getOpcode(), SDLoc(N), NVT, Op, N->getOperand(1));
+  else
+    return DAG.getNode(N->getOpcode(), SDLoc(N), NVT, Op);
 }
 
 // Binary operations where the result and both operands have PromoteFloat type
@@ -3245,6 +3251,8 @@ void DAGTypeLegalizer::SoftPromoteHalfResult(SDNode *N, unsigned ResNo) {
     report_fatal_error("Do not know how to soft promote this operator's "
                        "result!");
 
+  // case ISD::AssertNoFPClass:
+  //   break;
   case ISD::ARITH_FENCE:
     R = SoftPromoteHalfRes_ARITH_FENCE(N); break;
   case ISD::BITCAST:    R = SoftPromoteHalfRes_BITCAST(N); break;
@@ -3283,6 +3291,7 @@ void DAGTypeLegalizer::SoftPromoteHalfResult(SDNode *N, unsigned ResNo) {
   case ISD::FTRUNC:
   case ISD::FTAN:
   case ISD::FTANH:
+  case ISD::AssertNoFPClass:
   case ISD::FCANONICALIZE: R = SoftPromoteHalfRes_UnaryOp(N); break;
 
   // Binary FP Operations
@@ -3604,7 +3613,11 @@ SDValue DAGTypeLegalizer::SoftPromoteHalfRes_UnaryOp(SDNode *N) {
   // Promote to the larger FP type.
   Op = DAG.getNode(GetPromotionOpcode(OVT, NVT), dl, NVT, Op);
 
-  SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, Op);
+  SDValue Res;
+  if (N->getOpcode() == ISD::AssertNoFPClass)
+    Res = DAG.getNode(N->getOpcode(), dl, NVT, Op, N->getOperand(1));
+  else
+    Res = DAG.getNode(N->getOpcode(), dl, NVT, Op);
 
   // Convert back to FP16 as an integer.
   return DAG.getNode(GetPromotionOpcode(NVT, OVT), dl, MVT::i16, Res);

llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h

@@ -80,7 +80,9 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
   /// Pretend all of this node's results are legal.
   bool IgnoreNodeResults(SDNode *N) const {
     return N->getOpcode() == ISD::TargetConstant ||
-           N->getOpcode() == ISD::Register;
+           N->getOpcode() == ISD::Register ||
+           (N->getOpcode() == ISD::AssertNoFPClass &&
+            IgnoreNodeResults(N->getOperand(0).getNode()));
   }
 
   // Bijection from SDValue to unique id. As each created node gets a
@@ -796,6 +798,8 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
   //===--------------------------------------------------------------------===//
 
   SDValue GetSoftPromotedHalf(SDValue Op) {
+    while (Op.getNode()->getOpcode() == ISD::AssertNoFPClass)
+      Op = Op.getNode()->getOperand(0);
     TableId &PromotedId = SoftPromotedHalfs[getTableId(Op)];
     SDValue PromotedOp = getSDValue(PromotedId);
     assert(PromotedOp.getNode() && "Operand wasn't promoted?");

llvm/test/CodeGen/ARM/nofpclass.ll

@@ -0,0 +1,25 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=armv8-unknown-none-eabi < %s | FileCheck %s
+
+define nofpclass(nan inf) half @f1(half returned nofpclass(nan inf) %x) {
+; CHECK-LABEL: f1:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    bx lr
+entry:
+  ret half %x
+}
+
+define noundef half @f2(half nofpclass(nan) %a) {
+; CHECK-LABEL: f2:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmov.f32 s0, #1.000000e+00
+; CHECK-NEXT:    vmov s2, r0
+; CHECK-NEXT:    vcvtb.f32.f16 s2, s2
+; CHECK-NEXT:    vadd.f32 s0, s2, s0
+; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = fadd half %a, 0xH3C00
+  ret half %0
+}