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DAG: Combine AssertZext with and AssertSext
#142898 (comment)
1 parent 4b71e89 commit 232ebc7

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7 files changed

+40
-31
lines changed

7 files changed

+40
-31
lines changed

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14933,6 +14933,25 @@ SDValue DAGCombiner::visitAssertExt(SDNode *N) {
1493314933
}
1493414934
}
1493514935

14936+
// If we have (AssertZext (and (AssertSext X, iX), M), iY) and Y is smaller
14937+
// than X, and the And doesn't change the lower iY bits, we can move the
14938+
// AssertZext in front of the And and drop the AssertSext.
14939+
if (Opcode == ISD::AssertZext && N0.getOpcode() == ISD::AND &&
14940+
N0.hasOneUse() && N0.getOperand(0).getOpcode() == ISD::AssertSext &&
14941+
isa<ConstantSDNode>(N0.getOperand(1))) {
14942+
SDValue BigA = N0.getOperand(0);
14943+
EVT BigA_AssertVT = cast<VTSDNode>(BigA.getOperand(1))->getVT();
14944+
const APInt &Mask = N0.getConstantOperandAPInt(1);
14945+
if (AssertVT.bitsLT(BigA_AssertVT) &&
14946+
Mask.countr_one() >= AssertVT.getScalarSizeInBits()) {
14947+
SDLoc DL(N);
14948+
SDValue NewAssert =
14949+
DAG.getNode(Opcode, DL, N->getValueType(0), BigA.getOperand(0), N1);
14950+
return DAG.getNode(ISD::AND, DL, N->getValueType(0), NewAssert,
14951+
N0.getOperand(1));
14952+
}
14953+
}
14954+
1493614955
return SDValue();
1493714956
}
1493814957

‎llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -434,11 +434,7 @@ void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT,
434434

435435
EVT SetCCVT =
436436
getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), RetVT);
437-
if (RetVT == SetCCVT &&
438-
getBooleanContents(RetVT) == ZeroOrOneBooleanContent) {
439-
// FIXME: Checking the type matches is a hack in case the calling
440-
// convention lowering inserted some instructions after the
441-
// CopyFromReg. Combines fail to look through the AssertZext.
437+
if (getBooleanContents(RetVT) == ZeroOrOneBooleanContent) {
442438
NewLHS = DAG.getNode(ISD::AssertZext, dl, RetVT, Call.first,
443439
DAG.getValueType(MVT::i1));
444440
}

‎llvm/test/CodeGen/RISCV/double-fcmp-strict.ll

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -498,13 +498,13 @@ define i32 @fcmp_ueq(double %a, double %b) nounwind strictfp {
498498
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
499499
; RV64I-NEXT: mv s0, a1
500500
; RV64I-NEXT: mv s1, a0
501-
; RV64I-NEXT: call __eqdf2
502-
; RV64I-NEXT: seqz s2, a0
501+
; RV64I-NEXT: call __unorddf2
502+
; RV64I-NEXT: mv s2, a0
503503
; RV64I-NEXT: mv a0, s1
504504
; RV64I-NEXT: mv a1, s0
505-
; RV64I-NEXT: call __unorddf2
506-
; RV64I-NEXT: snez a0, a0
507-
; RV64I-NEXT: or a0, a0, s2
505+
; RV64I-NEXT: call __eqdf2
506+
; RV64I-NEXT: seqz a0, a0
507+
; RV64I-NEXT: or a0, s2, a0
508508
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
509509
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
510510
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
@@ -1226,13 +1226,13 @@ define i32 @fcmps_ueq(double %a, double %b) nounwind strictfp {
12261226
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
12271227
; RV64I-NEXT: mv s0, a1
12281228
; RV64I-NEXT: mv s1, a0
1229-
; RV64I-NEXT: call __eqdf2
1230-
; RV64I-NEXT: seqz s2, a0
1229+
; RV64I-NEXT: call __unorddf2
1230+
; RV64I-NEXT: mv s2, a0
12311231
; RV64I-NEXT: mv a0, s1
12321232
; RV64I-NEXT: mv a1, s0
1233-
; RV64I-NEXT: call __unorddf2
1234-
; RV64I-NEXT: snez a0, a0
1235-
; RV64I-NEXT: or a0, a0, s2
1233+
; RV64I-NEXT: call __eqdf2
1234+
; RV64I-NEXT: seqz a0, a0
1235+
; RV64I-NEXT: or a0, s2, a0
12361236
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
12371237
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
12381238
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload

‎llvm/test/CodeGen/RISCV/double-fcmp.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -430,13 +430,13 @@ define i32 @fcmp_ueq(double %a, double %b) nounwind {
430430
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
431431
; RV64I-NEXT: mv s0, a1
432432
; RV64I-NEXT: mv s1, a0
433-
; RV64I-NEXT: call __eqdf2
434-
; RV64I-NEXT: seqz s2, a0
433+
; RV64I-NEXT: call __unorddf2
434+
; RV64I-NEXT: mv s2, a0
435435
; RV64I-NEXT: mv a0, s1
436436
; RV64I-NEXT: mv a1, s0
437-
; RV64I-NEXT: call __unorddf2
438-
; RV64I-NEXT: snez a0, a0
439-
; RV64I-NEXT: or a0, a0, s2
437+
; RV64I-NEXT: call __eqdf2
438+
; RV64I-NEXT: seqz a0, a0
439+
; RV64I-NEXT: or a0, s2, a0
440440
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
441441
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
442442
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload

‎llvm/test/CodeGen/RISCV/float-fcmp.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -367,13 +367,13 @@ define i32 @fcmp_ueq(float %a, float %b) nounwind {
367367
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
368368
; RV64I-NEXT: mv s0, a1
369369
; RV64I-NEXT: mv s1, a0
370-
; RV64I-NEXT: call __eqsf2
371-
; RV64I-NEXT: seqz s2, a0
370+
; RV64I-NEXT: call __unordsf2
371+
; RV64I-NEXT: mv s2, a0
372372
; RV64I-NEXT: mv a0, s1
373373
; RV64I-NEXT: mv a1, s0
374-
; RV64I-NEXT: call __unordsf2
375-
; RV64I-NEXT: snez a0, a0
376-
; RV64I-NEXT: or a0, a0, s2
374+
; RV64I-NEXT: call __eqsf2
375+
; RV64I-NEXT: seqz a0, a0
376+
; RV64I-NEXT: or a0, s2, a0
377377
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
378378
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
379379
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload

‎llvm/test/CodeGen/X86/fp128-libcalls-strict.ll

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -3443,8 +3443,6 @@ define i64 @cmp_ueq_q(i64 %a, i64 %b, fp128 %x, fp128 %y) #0 {
34433443
; X86-NEXT: pushl {{[0-9]+}}(%esp)
34443444
; X86-NEXT: calll __unordtf2
34453445
; X86-NEXT: addl $32, %esp
3446-
; X86-NEXT: testl %eax, %eax
3447-
; X86-NEXT: setne %al
34483446
; X86-NEXT: orb %bl, %al
34493447
; X86-NEXT: leal {{[0-9]+}}(%esp), %eax
34503448
; X86-NEXT: leal {{[0-9]+}}(%esp), %ecx
@@ -3526,8 +3524,6 @@ define i64 @cmp_ueq_q(i64 %a, i64 %b, fp128 %x, fp128 %y) #0 {
35263524
; WIN-X86-NEXT: pushl {{[0-9]+}}(%esp)
35273525
; WIN-X86-NEXT: calll ___unordtf2
35283526
; WIN-X86-NEXT: addl $32, %esp
3529-
; WIN-X86-NEXT: testl %eax, %eax
3530-
; WIN-X86-NEXT: setne %al
35313527
; WIN-X86-NEXT: orb %bl, %al
35323528
; WIN-X86-NEXT: jne LBB39_1
35333529
; WIN-X86-NEXT: # %bb.2:

‎llvm/test/CodeGen/X86/fpcmp-soft-fp.ll

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -99,8 +99,6 @@ entry:
9999
; CHECK: calll __eqdf2
100100
; CHECK: sete
101101
; CHECK: calll __unorddf2
102-
; CHECK: setne
103-
; CHECK: or
104102
; CHECK: retl
105103

106104
define i1 @test11(double %d) #0 {

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