Skip to content

Commit 1c4caec

Browse files
authored
[Mips] Use APInt::isMask/isShiftedMask to simplify code. (#116582)
1 parent c9260e2 commit 1c4caec

File tree

1 file changed

+4
-8
lines changed

1 file changed

+4
-8
lines changed

llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp

Lines changed: 4 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -614,11 +614,9 @@ bool MipsSEDAGToDAGISel::selectVSplatMaskL(SDValue N, SDValue &Imm) const {
614614

615615
if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
616616
ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
617-
// Extract the run of set bits starting with bit zero from the bitwise
618-
// inverse of ImmValue, and test that the inverse of this is the same
619-
// as the original value.
620-
if (ImmValue == ~(~ImmValue & ~(~ImmValue + 1))) {
621-
617+
// Check if we have a leading one, then check if the whole value is a
618+
// shifted mask.
619+
if (ImmValue.isNegative() && ImmValue.isShiftedMask()) {
622620
Imm = CurDAG->getTargetConstant(ImmValue.popcount() - 1, SDLoc(N), EltTy);
623621
return true;
624622
}
@@ -647,9 +645,7 @@ bool MipsSEDAGToDAGISel::selectVSplatMaskR(SDValue N, SDValue &Imm) const {
647645

648646
if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
649647
ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
650-
// Extract the run of set bits starting with bit zero, and test that the
651-
// result is the same as the original value
652-
if (ImmValue == (ImmValue & ~(ImmValue + 1))) {
648+
if (ImmValue.isMask()) {
653649
Imm = CurDAG->getTargetConstant(ImmValue.popcount() - 1, SDLoc(N), EltTy);
654650
return true;
655651
}

0 commit comments

Comments
 (0)